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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// 1. Active edge of reset changed from High to Low
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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`include "top_defines.v"
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`include "top_defines.v"
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module oc8051_ram_top (clk,
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module oc8051_ram_top (clk,
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rst,
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resetn,
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rd_addr,
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rd_addr,
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rd_data,
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rd_data,
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wr_addr,
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wr_addr,
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bit_addr,
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bit_addr,
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wr_data,
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wr_data,
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Line 109... |
// wr (in) write [oc8051_decoder.wr -r]
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// wr (in) write [oc8051_decoder.wr -r]
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// bit_data_in (in) bit data input [oc8051_alu.desCy]
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// bit_data_in (in) bit data input [oc8051_alu.desCy]
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// bit_data_out (out) bit data output [oc8051_ram_sel.bit_in]
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// bit_data_out (out) bit data output [oc8051_ram_sel.bit_in]
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//
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//
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input clk, wr, bit_addr, bit_data_in, rst;
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input clk, wr, bit_addr, bit_data_in, resetn;
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input [7:0] wr_data;
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input [7:0] wr_data;
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input [7:0] rd_addr, wr_addr;
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input [7:0] rd_addr, wr_addr;
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output bit_data_out;
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output bit_data_out;
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output [7:0] rd_data;
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output [7:0] rd_data;
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assign rd_data = rd_en_r ? wr_data_r: rd_data_m;
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assign rd_data = rd_en_r ? wr_data_r: rd_data_m;
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assign rd_en = (rd_addr_m == wr_addr_m) & wr;
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assign rd_en = (rd_addr_m == wr_addr_m) & wr;
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oc8051_ram_256x8_two_bist u_ram_idata(
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oc8051_ram_256x8_two_bist u_ram_idata(
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.clk ( clk ),
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.clk ( clk ),
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.rst ( rst ),
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.resetn ( resetn ),
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.rd_addr ( rd_addr_m ),
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.rd_addr ( rd_addr_m ),
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.rd_data ( rd_data_m ),
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.rd_data ( rd_data_m ),
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.rd_en ( !rd_en ),
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.rd_en ( !rd_en ),
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.wr_addr ( wr_addr_m ),
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.wr_addr ( wr_addr_m ),
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.wr_data ( wr_data_m ),
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.wr_data ( wr_data_m ),
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Line 163... |
.scanb_so(scanb_so),
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.scanb_so(scanb_so),
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.scanb_en(scanb_en)
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.scanb_en(scanb_en)
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`endif
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`endif
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);
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);
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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if (rst) begin
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if (resetn == 1'b0) begin
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bit_addr_r <= #1 1'b0;
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bit_addr_r <= #1 1'b0;
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bit_select <= #1 3'b0;
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bit_select <= #1 3'b0;
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end else begin
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end else begin
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bit_addr_r <= #1 bit_addr;
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bit_addr_r <= #1 bit_addr;
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bit_select <= #1 rd_addr[2:0];
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bit_select <= #1 rd_addr[2:0];
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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if (rst) begin
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if (resetn == 1'b0) begin
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rd_en_r <= #1 1'b0;
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rd_en_r <= #1 1'b0;
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wr_data_r <= #1 8'h0;
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wr_data_r <= #1 8'h0;
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end else begin
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end else begin
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rd_en_r <= #1 rd_en;
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rd_en_r <= #1 rd_en;
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wr_data_r <= #1 wr_data_m;
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wr_data_r <= #1 wr_data_m;
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