Subversion Repositories oms8051mini

////  Author(s):                                                  ////

////  Author(s):                                                  ////

////      - Simon Teran, simont@opencores.org                     ////

////      - Simon Teran, simont@opencores.org                     ////

////      - Dinesh Annayya, dinesha@opencores.org                 ////

////      - Dinesh Annayya, dinesha@opencores.org                 ////

////                                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

////                                                              ////

////                                                              ////

//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////

//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////

////                                                              ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// restriction provided that this copyright statement is not    ////

// prepared header

// prepared header

//

//

//

//

`include "top_defines.v"

`include "top_defines.v"

//parameter INT_ROM_WID= 15;

//parameter INT_ROM_WID= 15;

input [15:0] addr;

input [15:0] addr;

//input [22:0] addr;

//input [22:0] addr;

output ea_int;

output ea_int;

output [31:0] data_o;

output [31:0] data_o;

wire [15:0] addr_rst;

wire [15:0] addr_rst;

wire [7:0] int_data0, int_data1, int_data2, int_data3, int_data4, int_data5, int_data6, int_data7, int_data8, int_data9, int_data10, int_data11, int_data12, int_data13, int_data14, int_data15, int_data16, int_data17, int_data18, int_data19, int_data20, int_data21, int_data22, int_data23, int_data24, int_data25, int_data26, int_data27, int_data28, int_data29, int_data30, int_data31, int_data32, int_data33, int_data34, int_data35, int_data36, int_data37, int_data38, int_data39, int_data40, int_data41, int_data42, int_data43, int_data44, int_data45, int_data46, int_data47, int_data48, int_data49, int_data50, int_data51, int_data52, int_data53, int_data54, int_data55, int_data56, int_data57, int_data58, int_data59, int_data60, int_data61, int_data62, int_data63, int_data64, int_data65, int_data66, int_data67, int_data68, int_data69, int_data70, int_data71, int_data72, int_data73, int_data74, int_data75, int_data76, int_data77, int_data78, int_data79, int_data80, int_data81, int_data82, int_data83, int_data84, int_data85, int_data86, int_data87, int_data88, int_data89, int_data90, int_data91, int_data92, int_data93, int_data94, int_data95, int_data96, int_data97, int_data98, int_data99, int_data100, int_data101, int_data102, int_data103, int_data104, int_data105, int_data106, int_data107, int_data108, int_data109, int_data110, int_data111, int_data112, int_data113, int_data114, int_data115, int_data116, int_data117, int_data118, int_data119, int_data120, int_data121, int_data122, int_data123, int_data124, int_data125, int_data126, int_data127;

wire [7:0] int_data0, int_data1, int_data2, int_data3, int_data4, int_data5, int_data6, int_data7, int_data8, int_data9, int_data10, int_data11, int_data12, int_data13, int_data14, int_data15, int_data16, int_data17, int_data18, int_data19, int_data20, int_data21, int_data22, int_data23, int_data24, int_data25, int_data26, int_data27, int_data28, int_data29, int_data30, int_data31, int_data32, int_data33, int_data34, int_data35, int_data36, int_data37, int_data38, int_data39, int_data40, int_data41, int_data42, int_data43, int_data44, int_data45, int_data46, int_data47, int_data48, int_data49, int_data50, int_data51, int_data52, int_data53, int_data54, int_data55, int_data56, int_data57, int_data58, int_data59, int_data60, int_data61, int_data62, int_data63, int_data64, int_data65, int_data66, int_data67, int_data68, int_data69, int_data70, int_data71, int_data72, int_data73, int_data74, int_data75, int_data76, int_data77, int_data78, int_data79, int_data80, int_data81, int_data82, int_data83, int_data84, int_data85, int_data86, int_data87, int_data88, int_data89, int_data90, int_data91, int_data92, int_data93, int_data94, int_data95, int_data96, int_data97, int_data98, int_data99, int_data100, int_data101, int_data102, int_data103, int_data104, int_data105, int_data106, int_data107, int_data108, int_data109, int_data110, int_data111, int_data112, int_data113, int_data114, int_data115, int_data116, int_data117, int_data118, int_data119, int_data120, int_data121, int_data122, int_data123, int_data124, int_data125, int_data126, int_data127;

assign ea = | addr[15:INT_ROM_WID];

assign ea = | addr[15:INT_ROM_WID];

  rom0 rom_0 (.a(addr01), .o(int_data0));

  rom0 rom_0 (.a(addr01), .o(int_data0));

  rom1 rom_1 (.a(addr01), .o(int_data1));

  rom1 rom_1 (.a(addr01), .o(int_data1));

  rom2 rom_2 (.a(addr_rst[11:7]), .o(int_data2));

  rom2 rom_2 (.a(addr_rst[11:7]), .o(int_data2));

  rom3 rom_3 (.a(addr_rst[11:7]), .o(int_data3));

  rom3 rom_3 (.a(addr_rst[11:7]), .o(int_data3));

      data3 <= #1 8'h00;

      data3 <= #1 8'h00;

        end

        end

  endcase

  endcase

end

end

   ea_int <= #1 1'b1;

   ea_int <= #1 1'b1;

  else ea_int <= #1 !ea;

  else ea_int <= #1 !ea;

`elsif OC8051_ACTEL_ROM

`elsif OC8051_ACTEL_ROM

initial

initial

begin

begin

  $readmemh("./dat/oc8051_xrom.in", buff);

  $readmemh("./dat/oc8051_xrom.in", buff);

end

end

   ea_int <= #1 1'b1;

   ea_int <= #1 1'b1;

  else ea_int <= #1 !ea;

  else ea_int <= #1 !ea;

always @(posedge clk)

always @(posedge clk)

begin

begin