OpenCores

Rev 2	Rev 25
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`//// Author(s): ////`	`//// Author(s): ////`
`//// - Simon Teran, simont@opencores.org ////`	`//// - Simon Teran, simont@opencores.org ////`
`//// - Dinesh Annayya, dinesha@opencores.org ////`	`//// - Dinesh Annayya, dinesha@opencores.org ////`
`//// ////`	`//// ////`
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
	`//// v0.0 - Dinesh A, 5th Jan 2017`
	`//// 1. Active edge of reset changed from High to Low`
	`//////////////////////////////////////////////////////////////////////`
`//// ////`	`//// ////`
`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`	`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
`//// ////`	`//// ////`
`//// This source file may be used and distributed without ////`	`//// This source file may be used and distributed without ////`
`//// restriction provided that this copyright statement is not ////`	`//// restriction provided that this copyright statement is not ////`
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`include "top_defines.v"	`include "top_defines.v"


`module oc8051_sfr (rst, clk,`	`module oc8051_sfr (resetn, clk,`
`adr0, adr1, dat0,`	`adr0, adr1, dat0,`
`dat1, dat2, bit_in,`	`dat1, dat2, bit_in,`
`des_acc,`	`des_acc,`
`we, wr_bit,`	`we, wr_bit,`
`bit_out,`	`bit_out,`
Line 153...	Line 156...

`dptr_hi, dptr_lo,`	`dptr_hi, dptr_lo,`
`wait_data);`	`wait_data);`


`input rst, // reset - pin`	`input resetn, // reset - pin`
`clk, // clock - pin`	`clk, // clock - pin`
`we, // write enable`	`we, // write enable`
`bit_in,`	`bit_in,`
`desAc,`	`desAc,`
`desOv,`	`desOv,`
Line 305...	Line 308...

`//`	`//`
`// accumulator`	`// accumulator`
`// ACC`	`// ACC`
`oc8051_acc oc8051_acc1(.clk(clk),`	`oc8051_acc oc8051_acc1(.clk(clk),`
`.rst(rst),`	`.resetn(resetn),`
`.bit_in(bit_in),`	`.bit_in(bit_in),`
`.data_in(des_acc),`	`.data_in(des_acc),`
`.data2_in(dat2),`	`.data2_in(dat2),`
`.wr(we),`	`.wr(we),`
`.wr_bit(wr_bit_r),`	`.wr_bit(wr_bit_r),`
Line 321...	Line 324...

`//`	`//`
`// b register`	`// b register`
`// B`	`// B`
`oc8051_b_register oc8051_b_register (.clk(clk),`	`oc8051_b_register oc8051_b_register (.clk(clk),`
`.rst(rst),`	`.resetn(resetn),`
`.bit_in(bit_in),`	`.bit_in(bit_in),`
`.data_in(des_acc),`	`.data_in(des_acc),`
`.wr(we),`	`.wr(we),`
`.wr_bit(wr_bit_r),`	`.wr_bit(wr_bit_r),`
`.wr_addr(adr1),`	`.wr_addr(adr1),`
Line 333...	Line 336...

`//`	`//`
`//stack pointer`	`//stack pointer`
`// SP`	`// SP`
`oc8051_sp oc8051_sp1(.clk(clk),`	`oc8051_sp oc8051_sp1(.clk(clk),`
`.rst(rst),`	`.resetn(resetn),`
`.ram_rd_sel(ram_rd_sel),`	`.ram_rd_sel(ram_rd_sel),`
`.ram_wr_sel(ram_wr_sel),`	`.ram_wr_sel(ram_wr_sel),`
`.wr_addr(adr1),`	`.wr_addr(adr1),`
`.wr(we),`	`.wr(we),`
`.wr_bit(wr_bit_r),`	`.wr_bit(wr_bit_r),`
Line 347...	Line 350...

`//`	`//`
`//data pointer`	`//data pointer`
`// DPTR, DPH, DPL`	`// DPTR, DPH, DPL`
`oc8051_dptr oc8051_dptr1(.clk(clk),`	`oc8051_dptr oc8051_dptr1(.clk(clk),`
`.rst(rst),`	`.resetn(resetn),`
`.addr(adr1),`	`.addr(adr1),`
`.data_in(des_acc),`	`.data_in(des_acc),`
`.data2_in(dat2),`	`.data2_in(dat2),`
`.wr(we),`	`.wr(we),`
`.wr_bit(wr_bit_r),`	`.wr_bit(wr_bit_r),`
Line 362...	Line 365...

`//`	`//`
`//program status word`	`//program status word`
`// PSW`	`// PSW`
`oc8051_psw oc8051_psw1 (.clk(clk),`	`oc8051_psw oc8051_psw1 (.clk(clk),`
`.rst(rst),`	`.resetn(resetn),`
`.wr_addr(adr1),`	`.wr_addr(adr1),`
`.data_in(dat1),`	`.data_in(dat1),`
`.wr(we),`	`.wr(we),`
`.wr_bit(wr_bit_r),`	`.wr_bit(wr_bit_r),`
`.data_out(psw),`	`.data_out(psw),`
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`//`	`//`
`// ports`	`// ports`
`// P0, P1, P2, P3`	`// P0, P1, P2, P3`
`ifdef OC8051_PORTS	`ifdef OC8051_PORTS
`oc8051_ports oc8051_ports1(.clk(clk),`	`oc8051_ports oc8051_ports1(.clk(clk),`
`.rst(rst),`	`.resetn(resetn),`
`.bit_in(bit_in),`	`.bit_in(bit_in),`
`.data_in(dat1),`	`.data_in(dat1),`
`.wr(we),`	`.wr(we),`
`.wr_bit(wr_bit_r),`	`.wr_bit(wr_bit_r),`
`.wr_addr(adr1),`	`.wr_addr(adr1),`
Line 419...	Line 422...
`//`	`//`
`// serial interface`	`// serial interface`
`// SCON, SBUF`	`// SCON, SBUF`
`ifdef OC8051_UART	`ifdef OC8051_UART
`oc8051_uart oc8051_uatr1 (.clk(clk),`	`oc8051_uart oc8051_uatr1 (.clk(clk),`
`.rst(rst),`	`.resetn(resetn),`
`.bit_in(bit_in),`	`.bit_in(bit_in),`
`.data_in(dat1),`	`.data_in(dat1),`
`.wr(we),`	`.wr(we),`
`.wr_bit(wr_bit_r),`	`.wr_bit(wr_bit_r),`
`.wr_addr(adr1),`	`.wr_addr(adr1),`
Line 447...	Line 450...

`//`	`//`
`// interrupt control`	`// interrupt control`
`// IP, IE, TCON`	`// IP, IE, TCON`
`oc8051_int oc8051_int1 (.clk(clk),`	`oc8051_int oc8051_int1 (.clk(clk),`
`.rst(rst),`	`.resetn(resetn),`
`.wr_addr(adr1),`	`.wr_addr(adr1),`
`.bit_in(bit_in),`	`.bit_in(bit_in),`
`.ack(int_ack),`	`.ack(int_ack),`
`.data_in(dat1),`	`.data_in(dat1),`
`.wr(we),`	`.wr(we),`
Line 475...	Line 478...
`//`	`//`
`// timer/counter control`	`// timer/counter control`
`// TH0, TH1, TL0, TH1, TMOD`	`// TH0, TH1, TL0, TH1, TMOD`
`ifdef OC8051_TC01	`ifdef OC8051_TC01
`oc8051_tc oc8051_tc1(.clk(clk),`	`oc8051_tc oc8051_tc1(.clk(clk),`
`.rst(rst),`	`.resetn(resetn),`
`.wr_addr(adr1),`	`.wr_addr(adr1),`
`.data_in(dat1),`	`.data_in(dat1),`
`.wr(we),`	`.wr(we),`
`.wr_bit(wr_bit_r),`	`.wr_bit(wr_bit_r),`
`.ie0(int0),`	`.ie0(int0),`
Line 504...	Line 507...
`//`	`//`
`// timer/counter 2`	`// timer/counter 2`
`// TH2, TL2, RCAPL2L, RCAPL2H, T2CON`	`// TH2, TL2, RCAPL2L, RCAPL2H, T2CON`
`ifdef OC8051_TC2	`ifdef OC8051_TC2
`oc8051_tc2 oc8051_tc21(.clk(clk),`	`oc8051_tc2 oc8051_tc21(.clk(clk),`
`.rst(rst),`	`.resetn(resetn),`
`.wr_addr(adr1),`	`.wr_addr(adr1),`
`.data_in(dat1),`	`.data_in(dat1),`
`.wr(we),`	`.wr(we),`
`.wr_bit(wr_bit_r),`	`.wr_bit(wr_bit_r),`
`.bit_in(bit_in),`	`.bit_in(bit_in),`
Line 531...	Line 534...
`assign brate2 = 1'b0;`	`assign brate2 = 1'b0;`
`endif	`endif



`always @(posedge clk or posedge rst)`	`always @(posedge clk or negedge resetn)`
`if (rst) begin`	`if (resetn == 1'b0) begin`
`adr0_r <= #1 8'h00;`	`adr0_r <= #1 8'h00;`
`ram_wr_sel_r <= #1 3'b000;`	`ram_wr_sel_r <= #1 3'b000;`
`wr_bit_r <= #1 1'b0;`	`wr_bit_r <= #1 1'b0;`
`// wait_data <= #1 1'b0;`	`// wait_data <= #1 1'b0;`
`end else begin`	`end else begin`
Line 561...	Line 564...



`//`	`//`
`//set output in case of address (byte)`	`//set output in case of address (byte)`
`always @(posedge clk or posedge rst)`	`always @(posedge clk or negedge resetn)`
`begin`	`begin`
`if (rst) begin`	`if (resetn == 1'b0) begin`
`dat0 <= #1 8'h00;`	`dat0 <= #1 8'h00;`
`wait_data <= #1 1'b0;`	`wait_data <= #1 1'b0;`
end else if ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) begin //write and read same address	end else if ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) begin //write and read same address
`dat0 <= #1 des_acc;`	`dat0 <= #1 des_acc;`
`wait_data <= #1 1'b0;`	`wait_data <= #1 1'b0;`
Line 649...	Line 652...


`//`	`//`
`//set output in case of address (bit)`	`//set output in case of address (bit)`

`always @(posedge clk or posedge rst)`	`always @(posedge clk or negedge resetn)`
`begin`	`begin`
`if (rst)`	`if (resetn == 1'b0)`
`bit_out <= #1 1'h0;`	`bit_out <= #1 1'h0;`
`else if (`	`else if (`
`((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) & we & !wr_bit_r) \|`	`((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) & we & !wr_bit_r) \|`
((wr_sfr==`OC8051_WRS_ACC1) & (adr0[7:3]==`OC8051_SFR_B_ACC)) //write to acc	((wr_sfr==`OC8051_WRS_ACC1) & (adr0[7:3]==`OC8051_SFR_B_ACC)) //write to acc
`)`	`)`
Line 701...	Line 704...

`// default: bit_out <= #1 1'b0;`	`// default: bit_out <= #1 1'b0;`
`endcase`	`endcase`
`end`	`end`

`always @(posedge clk or posedge rst)`	`always @(posedge clk or negedge resetn)`
`begin`	`begin`
`if (rst) begin`	`if (resetn == 1'b0) begin`
`prescaler <= #1 4'h0;`	`prescaler <= #1 4'h0;`
`pres_ow <= #1 1'b0;`	`pres_ow <= #1 1'b0;`
`end else if (prescaler==4'b1011) begin`	`end else if (prescaler==4'b1011) begin`
`prescaler <= #1 4'h0;`	`prescaler <= #1 4'h0;`
`pres_ow <= #1 1'b1;`	`pres_ow <= #1 1'b1;`

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////  Author(s):                                                  ////

////  Author(s):                                                  ////

////      - Simon Teran, simont@opencores.org                     ////

////      - Simon Teran, simont@opencores.org                     ////

////      - Dinesh Annayya, dinesha@opencores.org                 ////

////      - Dinesh Annayya, dinesha@opencores.org                 ////

////                                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

////   v0.0 - Dinesh A, 5th Jan 2017

////        1. Active edge of reset changed from High to Low

//////////////////////////////////////////////////////////////////////

////                                                              ////

////                                                              ////

//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////

//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////

////                                                              ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// restriction provided that this copyright statement is not    ////

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`include "top_defines.v"

`include "top_defines.v"

module oc8051_sfr (rst, clk,

module oc8051_sfr (resetn, clk,

       adr0, adr1, dat0,

       adr0, adr1, dat0,

       dat1, dat2, bit_in,

       dat1, dat2, bit_in,

       des_acc,

       des_acc,

       we, wr_bit,

       we, wr_bit,

       bit_out,

       bit_out,

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       dptr_hi, dptr_lo,

       dptr_hi, dptr_lo,

       wait_data);

       wait_data);

input       rst,        // reset - pin

input       resetn,     // reset - pin

            clk,        // clock - pin

            clk,        // clock - pin

            we,         // write enable

            we,         // write enable

            bit_in,

            bit_in,

            desAc,

            desAc,

            desOv,

            desOv,

Line 305...

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//

//

// accumulator

// accumulator

// ACC

// ACC

oc8051_acc oc8051_acc1(.clk(clk),

oc8051_acc oc8051_acc1(.clk(clk),

                       .rst(rst),

                       .resetn(resetn),

                       .bit_in(bit_in),

                       .bit_in(bit_in),

                       .data_in(des_acc),

                       .data_in(des_acc),

                       .data2_in(dat2),

                       .data2_in(dat2),

                       .wr(we),

                       .wr(we),

                       .wr_bit(wr_bit_r),

                       .wr_bit(wr_bit_r),

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//

//

// b register

// b register

// B

// B

oc8051_b_register oc8051_b_register (.clk(clk),

oc8051_b_register oc8051_b_register (.clk(clk),

                                     .rst(rst),

                                     .resetn(resetn),

                                     .bit_in(bit_in),

                                     .bit_in(bit_in),

                                     .data_in(des_acc),

                                     .data_in(des_acc),

                                     .wr(we),

                                     .wr(we),

                                     .wr_bit(wr_bit_r),

                                     .wr_bit(wr_bit_r),

                                     .wr_addr(adr1),

                                     .wr_addr(adr1),

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//

//

//stack pointer

//stack pointer

// SP

// SP

oc8051_sp oc8051_sp1(.clk(clk),

oc8051_sp oc8051_sp1(.clk(clk),

                     .rst(rst),

                     .resetn(resetn),

                     .ram_rd_sel(ram_rd_sel),

                     .ram_rd_sel(ram_rd_sel),

                     .ram_wr_sel(ram_wr_sel),

                     .ram_wr_sel(ram_wr_sel),

                     .wr_addr(adr1),

                     .wr_addr(adr1),

                     .wr(we),

                     .wr(we),

                     .wr_bit(wr_bit_r),

                     .wr_bit(wr_bit_r),

Line 347...

Line 350...

//

//

//data pointer

//data pointer

// DPTR, DPH, DPL

// DPTR, DPH, DPL

oc8051_dptr oc8051_dptr1(.clk(clk),

oc8051_dptr oc8051_dptr1(.clk(clk),

                         .rst(rst),

                         .resetn(resetn),

                         .addr(adr1),

                         .addr(adr1),

                         .data_in(des_acc),

                         .data_in(des_acc),

                         .data2_in(dat2),

                         .data2_in(dat2),

                         .wr(we),

                         .wr(we),

                         .wr_bit(wr_bit_r),

                         .wr_bit(wr_bit_r),

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//

//

//program status word

//program status word

// PSW

// PSW

oc8051_psw oc8051_psw1 (.clk(clk),

oc8051_psw oc8051_psw1 (.clk(clk),

                        .rst(rst),

                        .resetn(resetn),

                        .wr_addr(adr1),

                        .wr_addr(adr1),

                        .data_in(dat1),

                        .data_in(dat1),

                        .wr(we),

                        .wr(we),

                        .wr_bit(wr_bit_r),

                        .wr_bit(wr_bit_r),

                        .data_out(psw),

                        .data_out(psw),

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//

//

// ports

// ports

// P0, P1, P2, P3

// P0, P1, P2, P3

`ifdef OC8051_PORTS

`ifdef OC8051_PORTS

  oc8051_ports oc8051_ports1(.clk(clk),

  oc8051_ports oc8051_ports1(.clk(clk),

                           .rst(rst),

                           .resetn(resetn),

                           .bit_in(bit_in),

                           .bit_in(bit_in),

                           .data_in(dat1),

                           .data_in(dat1),

                           .wr(we),

                           .wr(we),

                           .wr_bit(wr_bit_r),

                           .wr_bit(wr_bit_r),

                           .wr_addr(adr1),

                           .wr_addr(adr1),

Line 419...

Line 422...

//

//

// serial interface

// serial interface

// SCON, SBUF

// SCON, SBUF

`ifdef OC8051_UART

`ifdef OC8051_UART

  oc8051_uart oc8051_uatr1 (.clk(clk),

  oc8051_uart oc8051_uatr1 (.clk(clk),

                            .rst(rst),

                            .resetn(resetn),

                            .bit_in(bit_in),

                            .bit_in(bit_in),

                            .data_in(dat1),

                            .data_in(dat1),

                            .wr(we),

                            .wr(we),

                            .wr_bit(wr_bit_r),

                            .wr_bit(wr_bit_r),

                            .wr_addr(adr1),

                            .wr_addr(adr1),

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//

//

// interrupt control

// interrupt control

// IP, IE, TCON

// IP, IE, TCON

oc8051_int oc8051_int1 (.clk(clk),

oc8051_int oc8051_int1 (.clk(clk),

                        .rst(rst),

                        .resetn(resetn),

                        .wr_addr(adr1),

                        .wr_addr(adr1),

                        .bit_in(bit_in),

                        .bit_in(bit_in),

                        .ack(int_ack),

                        .ack(int_ack),

                        .data_in(dat1),

                        .data_in(dat1),

                        .wr(we),

                        .wr(we),

Line 475...

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//

//

// timer/counter control

// timer/counter control

// TH0, TH1, TL0, TH1, TMOD

// TH0, TH1, TL0, TH1, TMOD

`ifdef OC8051_TC01

`ifdef OC8051_TC01

  oc8051_tc oc8051_tc1(.clk(clk),

  oc8051_tc oc8051_tc1(.clk(clk),

                       .rst(rst),

                       .resetn(resetn),

                       .wr_addr(adr1),

                       .wr_addr(adr1),

                       .data_in(dat1),

                       .data_in(dat1),

                       .wr(we),

                       .wr(we),

                       .wr_bit(wr_bit_r),

                       .wr_bit(wr_bit_r),

                       .ie0(int0),

                       .ie0(int0),

Line 504...

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//

//

// timer/counter 2

// timer/counter 2

// TH2, TL2, RCAPL2L, RCAPL2H, T2CON

// TH2, TL2, RCAPL2L, RCAPL2H, T2CON

`ifdef OC8051_TC2

`ifdef OC8051_TC2

  oc8051_tc2 oc8051_tc21(.clk(clk),

  oc8051_tc2 oc8051_tc21(.clk(clk),

                         .rst(rst),

                         .resetn(resetn),

                         .wr_addr(adr1),

                         .wr_addr(adr1),

                         .data_in(dat1),

                         .data_in(dat1),

                         .wr(we),

                         .wr(we),

                         .wr_bit(wr_bit_r),

                         .wr_bit(wr_bit_r),

                         .bit_in(bit_in),

                         .bit_in(bit_in),

Line 531...

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  assign brate2  = 1'b0;

  assign brate2  = 1'b0;

`endif

`endif

always @(posedge clk or posedge rst)

always @(posedge clk or negedge resetn)

  if (rst) begin

  if (resetn == 1'b0) begin

    adr0_r <= #1 8'h00;

    adr0_r <= #1 8'h00;

    ram_wr_sel_r <= #1 3'b000;

    ram_wr_sel_r <= #1 3'b000;

    wr_bit_r <= #1 1'b0;

    wr_bit_r <= #1 1'b0;

//    wait_data <= #1 1'b0;

//    wait_data <= #1 1'b0;

  end else begin

  end else begin

Line 561...

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//

//

//set output in case of address (byte)

//set output in case of address (byte)

always @(posedge clk or posedge rst)

always @(posedge clk or negedge resetn)

begin

begin

  if (rst) begin

  if (resetn == 1'b0) begin

    dat0 <= #1 8'h00;

    dat0 <= #1 8'h00;

    wait_data <= #1 1'b0;

    wait_data <= #1 1'b0;

  end else if ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) begin                          //write and read same address

  end else if ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) begin                          //write and read same address

    dat0 <= #1 des_acc;

    dat0 <= #1 des_acc;

    wait_data <= #1 1'b0;

    wait_data <= #1 1'b0;

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//

//

//set output in case of address (bit)

//set output in case of address (bit)

always @(posedge clk or posedge rst)

always @(posedge clk or negedge resetn)

begin

begin

  if (rst)

  if (resetn == 1'b0)

    bit_out <= #1 1'h0;

    bit_out <= #1 1'h0;

  else if (

  else if (

          ((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) &  we & !wr_bit_r) |

          ((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) &  we & !wr_bit_r) |

          ((wr_sfr==`OC8051_WRS_ACC1) & (adr0[7:3]==`OC8051_SFR_B_ACC))         //write to acc

          ((wr_sfr==`OC8051_WRS_ACC1) & (adr0[7:3]==`OC8051_SFR_B_ACC))         //write to acc

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//      default:             bit_out <= #1 1'b0;

//      default:             bit_out <= #1 1'b0;

    endcase

    endcase

end

end

always @(posedge clk or posedge rst)

always @(posedge clk or negedge resetn)

begin

begin

  if (rst) begin

  if (resetn == 1'b0) begin

    prescaler <= #1 4'h0;

    prescaler <= #1 4'h0;

    pres_ow <= #1 1'b0;

    pres_ow <= #1 1'b0;

  end else if (prescaler==4'b1011) begin

  end else if (prescaler==4'b1011) begin

    prescaler <= #1 4'h0;

    prescaler <= #1 4'h0;

    pres_ow <= #1 1'b1;

    pres_ow <= #1 1'b1;

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