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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// 1. Active edge of reset changed from High to Low
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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`include "top_defines.v"
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`include "top_defines.v"
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module oc8051_sp (clk, rst, ram_rd_sel, ram_wr_sel, wr_addr, wr, wr_bit, data_in, sp_out, sp_w);
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module oc8051_sp (clk, resetn, ram_rd_sel, ram_wr_sel, wr_addr, wr, wr_bit, data_in, sp_out, sp_w);
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input clk, rst, wr, wr_bit;
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input clk, resetn, wr, wr_bit;
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input [2:0] ram_rd_sel, ram_wr_sel;
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input [2:0] ram_rd_sel, ram_wr_sel;
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input [7:0] data_in, wr_addr;
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input [7:0] data_in, wr_addr;
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output [7:0] sp_out, sp_w;
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output [7:0] sp_out, sp_w;
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reg [7:0] sp_out, sp_w;
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reg [7:0] sp_out, sp_w;
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assign write = ((wr_addr==`OC8051_SFR_SP) & (wr) & !(wr_bit));
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assign write = ((wr_addr==`OC8051_SFR_SP) & (wr) & !(wr_bit));
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assign sp_t= write ? data_in : sp;
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assign sp_t= write ? data_in : sp;
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (rst)
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if (resetn == 1'b0)
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sp <= #1 `OC8051_RST_SP;
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sp <= #1 `OC8051_RST_SP;
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else if (write)
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else if (write)
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sp <= #1 data_in;
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sp <= #1 data_in;
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else
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else
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sp <= #1 sp_out;
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sp <= #1 sp_out;
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else sp_out = sp_t - {7'b0, pop};
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else sp_out = sp_t - {7'b0, pop};
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (rst)
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if (resetn == 1'b0)
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pop <= #1 1'b0;
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pop <= #1 1'b0;
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else if (ram_rd_sel==`OC8051_RRS_SP) pop <= #1 1'b1;
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else if (ram_rd_sel==`OC8051_RRS_SP) pop <= #1 1'b1;
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else pop <= #1 1'b0;
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else pop <= #1 1'b0;
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end
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end
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