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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// 1. Active edge of reset changed from High to Low
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//// 1. Active edge of reset changed from High to Low
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//// v0.1 - Dinesh A, 6th Jan 2017
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//// 1. pc_next logic added
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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`include "top_defines.v"
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`include "top_defines.v"
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module oc8051_sp (clk, resetn, ram_rd_sel, ram_wr_sel, wr_addr, wr, wr_bit, data_in, sp_out, sp_w);
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module oc8051_sp (
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// General I/F
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clk,
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resetn,
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ram_rd_sel,
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ram_wr_sel,
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// SP Reg Write I/F
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wr_addr,
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wr,
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wr_bit,
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data_in,
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sp_out,
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sp_w);
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input clk, resetn, wr, wr_bit;
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input clk, resetn, wr, wr_bit;
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input [2:0] ram_rd_sel, ram_wr_sel;
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input [2:0] ram_rd_sel, ram_wr_sel;
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input [7:0] data_in, wr_addr;
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input [7:0] data_in, wr_addr;
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