| Line 16... |
Line 16... |
//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// 1. Active edge of reset changed from High to Low
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//// 1. Active edge of reset changed from High to Low
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//// v0.1 - Dinesh A, 19th Jan 2017
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//// 1. Lint Warning fixes
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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| Line 116... |
Line 118... |
// read or write from one of the addresses in tmod
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// read or write from one of the addresses in tmod
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//
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//
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always @(posedge clk or negedge resetn)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (resetn == 1'b0) begin
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if (resetn == 1'b0) begin
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tmod <=#1 `OC8051_RST_TMOD;
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tmod <=`OC8051_RST_TMOD;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TMOD))
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TMOD))
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tmod <= #1 data_in;
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tmod <= data_in;
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end
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end
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//
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//
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// TIMER COUNTER 0
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// TIMER COUNTER 0
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//
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//
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always @(posedge clk or negedge resetn)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (resetn == 1'b0) begin
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if (resetn == 1'b0) begin
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tl0 <=#1 `OC8051_RST_TL0;
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tl0 <=`OC8051_RST_TL0;
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th0 <=#1 `OC8051_RST_TH0;
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th0 <=`OC8051_RST_TH0;
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tf0 <= #1 1'b0;
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tf0 <= 1'b0;
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tf1_0 <= #1 1'b0;
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tf1_0 <= 1'b0;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL0)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL0)) begin
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tl0 <= #1 data_in;
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tl0 <= data_in;
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tf0 <= #1 1'b0;
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tf0 <= 1'b0;
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tf1_0 <= #1 1'b0;
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tf1_0 <= 1'b0;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH0)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH0)) begin
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th0 <= #1 data_in;
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th0 <= data_in;
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tf0 <= #1 1'b0;
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tf0 <= 1'b0;
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tf1_0 <= #1 1'b0;
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tf1_0 <= 1'b0;
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end else begin
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end else begin
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case (tmod[1:0]) /* synopsys full_case parallel_case */
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case (tmod[1:0]) /* synopsys full_case parallel_case */
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`OC8051_MODE0: begin // mode 0
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`OC8051_MODE0: begin // mode 0
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tf1_0 <= #1 1'b0;
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tf1_0 <= 1'b0;
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if (tc0_add)
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if (tc0_add)
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{tf0, th0,tl0[4:0]} <= #1 {1'b0, th0, tl0[4:0]}+ 1'b1;
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{tf0, th0,tl0[4:0]} <= {1'b0, th0, tl0[4:0]}+ 1'b1;
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end
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end
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`OC8051_MODE1: begin // mode 1
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`OC8051_MODE1: begin // mode 1
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tf1_0 <= #1 1'b0;
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tf1_0 <= 1'b0;
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if (tc0_add)
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if (tc0_add)
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{tf0, th0,tl0} <= #1 {1'b0, th0, tl0}+ 1'b1;
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{tf0, th0,tl0} <= {1'b0, th0, tl0}+ 1'b1;
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end
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end
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|
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`OC8051_MODE2: begin // mode 2
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`OC8051_MODE2: begin // mode 2
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tf1_0 <= #1 1'b0;
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tf1_0 <= 1'b0;
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if (tc0_add) begin
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if (tc0_add) begin
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if (tl0 == 8'b1111_1111) begin
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if (tl0 == 8'b1111_1111) begin
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tf0 <=#1 1'b1;
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tf0 <=1'b1;
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tl0 <=#1 th0;
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tl0 <=th0;
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end
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end
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else begin
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else begin
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tl0 <=#1 tl0 + 8'h1;
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tl0 <=tl0 + 8'h1;
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tf0 <= #1 1'b0;
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tf0 <= 1'b0;
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end
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end
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end
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end
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end
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end
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`OC8051_MODE3: begin // mode 3
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`OC8051_MODE3: begin // mode 3
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|
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if (tc0_add)
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if (tc0_add)
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{tf0, tl0} <= #1 {1'b0, tl0} +1'b1;
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{tf0, tl0} <= {1'b0, tl0} +1'b1;
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|
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if (tr1 & pres_ow)
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if (tr1 & pres_ow)
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{tf1_0, th0} <= #1 {1'b0, th0} +1'b1;
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{tf1_0, th0} <= {1'b0, th0} +1'b1;
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|
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end
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end
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/* default:begin
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/* default:begin
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tf0 <= #1 1'b0;
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tf0 <= 1'b0;
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tf1_0 <= #1 1'b0;
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tf1_0 <= 1'b0;
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end*/
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end*/
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endcase
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endcase
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end
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end
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end
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end
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|
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| Line 188... |
Line 190... |
// TIMER COUNTER 1
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// TIMER COUNTER 1
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//
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//
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always @(posedge clk or negedge resetn)
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always @(posedge clk or negedge resetn)
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begin
|
begin
|
if (resetn == 1'b0) begin
|
if (resetn == 1'b0) begin
|
tl1 <=#1 `OC8051_RST_TL1;
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tl1 <=`OC8051_RST_TL1;
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th1 <=#1 `OC8051_RST_TH1;
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th1 <=`OC8051_RST_TH1;
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tf1_1 <= #1 1'b0;
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tf1_1 <= 1'b0;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL1)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL1)) begin
|
tl1 <= #1 data_in;
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tl1 <= data_in;
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tf1_1 <= #1 1'b0;
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tf1_1 <= 1'b0;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH1)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH1)) begin
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th1 <= #1 data_in;
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th1 <= data_in;
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tf1_1 <= #1 1'b0;
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tf1_1 <= 1'b0;
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end else begin
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end else begin
|
case (tmod[5:4]) /* synopsys full_case parallel_case */
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case (tmod[5:4]) /* synopsys full_case parallel_case */
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`OC8051_MODE0: begin // mode 0
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`OC8051_MODE0: begin // mode 0
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if (tc1_add)
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if (tc1_add)
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{tf1_1, th1,tl1[4:0]} <= #1 {1'b0, th1, tl1[4:0]}+ 1'b1;
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{tf1_1, th1,tl1[4:0]} <= {1'b0, th1, tl1[4:0]}+ 1'b1;
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end
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end
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`OC8051_MODE1: begin // mode 1
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`OC8051_MODE1: begin // mode 1
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if (tc1_add)
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if (tc1_add)
|
{tf1_1, th1,tl1} <= #1 {1'b0, th1, tl1}+ 1'b1;
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{tf1_1, th1,tl1} <= {1'b0, th1, tl1}+ 1'b1;
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end
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end
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|
|
`OC8051_MODE2: begin // mode 2
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`OC8051_MODE2: begin // mode 2
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if (tc1_add) begin
|
if (tc1_add) begin
|
if (tl1 == 8'b1111_1111) begin
|
if (tl1 == 8'b1111_1111) begin
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tf1_1 <=#1 1'b1;
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tf1_1 <=1'b1;
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tl1 <=#1 th1;
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tl1 <=th1;
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end
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end
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else begin
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else begin
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tl1 <=#1 tl1 + 8'h1;
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tl1 <=tl1 + 8'h1;
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tf1_1 <= #1 1'b0;
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tf1_1 <= 1'b0;
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end
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end
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end
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end
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end
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end
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/* default:begin
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default:begin
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tf1_1 <= #1 1'b0;
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tf1_1 <= 1'b0;
|
end*/
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end
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endcase
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endcase
|
end
|
end
|
end
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end
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|
|
|
|
always @(posedge clk or negedge resetn)
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always @(posedge clk or negedge resetn)
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if (resetn == 1'b0) begin
|
if (resetn == 1'b0) begin
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t0_buff <= #1 1'b0;
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t0_buff <= 1'b0;
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t1_buff <= #1 1'b0;
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t1_buff <= 1'b0;
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end else begin
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end else begin
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t0_buff <= #1 t0;
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t0_buff <= t0;
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t1_buff <= #1 t1;
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t1_buff <= t1;
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end
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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