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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// 1. Active edge of reset changed from High to Low
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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Line 59... |
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`include "top_defines.v"
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`include "top_defines.v"
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module oc8051_tc2 (clk, rst,
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module oc8051_tc2 (clk, resetn,
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wr_addr,
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wr_addr,
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data_in, bit_in,
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data_in, bit_in,
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wr, wr_bit,
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wr, wr_bit,
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t2, t2ex,
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t2, t2ex,
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rclk, tclk,
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rclk, tclk,
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Line 73... |
t2con, tl2, th2, rcap2l, rcap2h);
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t2con, tl2, th2, rcap2l, rcap2h);
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input [7:0] wr_addr,
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input [7:0] wr_addr,
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data_in;
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data_in;
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input clk,
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input clk,
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rst,
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resetn,
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wr,
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wr,
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wr_bit,
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wr_bit,
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t2,
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t2,
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t2ex,
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t2ex,
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bit_in,
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bit_in,
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Line 112... |
assign exen2 = t2con[3];
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assign exen2 = t2con[3];
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assign tr2 = t2con[2];
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assign tr2 = t2con[2];
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assign ct2 = t2con[1];
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assign ct2 = t2con[1];
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assign cprl2 = t2con[0];
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assign cprl2 = t2con[0];
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (rst) begin
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if (resetn == 1'b0) begin
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t2con <= #1 `OC8051_RST_T2CON;
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t2con <= #1 `OC8051_RST_T2CON;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_T2CON)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_T2CON)) begin
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t2con <= #1 data_in;
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t2con <= #1 data_in;
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end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_T2CON)) begin
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end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_T2CON)) begin
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t2con[wr_addr[2:0]] <= #1 bit_in;
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t2con[wr_addr[2:0]] <= #1 bit_in;
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Line 132... |
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//
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//
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//th2, tl2
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//th2, tl2
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assign run = tr2 & ((!ct2 & pres_ow) | (ct2 & tc2_event));
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assign run = tr2 & ((!ct2 & pres_ow) | (ct2 & tc2_event));
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (rst) begin
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if (resetn == 1'b0) begin
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//
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//
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// reset
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// reset
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//
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//
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tl2 <= #1 `OC8051_RST_TL2;
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tl2 <= #1 `OC8051_RST_TL2;
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th2 <= #1 `OC8051_RST_TH2;
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th2 <= #1 `OC8051_RST_TH2;
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Line 195... |
end
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end
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//
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//
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// rcap2l, rcap2h
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// rcap2l, rcap2h
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (rst) begin
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if (resetn == 1'b0) begin
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rcap2l <= #1 `OC8051_RST_RCAP2L;
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rcap2l <= #1 `OC8051_RST_RCAP2L;
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rcap2h <= #1 `OC8051_RST_RCAP2H;
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rcap2h <= #1 `OC8051_RST_RCAP2H;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_RCAP2H)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_RCAP2H)) begin
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rcap2h <= #1 data_in;
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rcap2h <= #1 data_in;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_RCAP2L)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_RCAP2L)) begin
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Line 213... |
end
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end
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//
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//
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (rst) begin
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if (resetn == 1'b0) begin
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neg_trans <= #1 1'b0;
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neg_trans <= #1 1'b0;
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t2ex_r <= #1 1'b0;
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t2ex_r <= #1 1'b0;
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end else if (t2ex) begin
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end else if (t2ex) begin
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neg_trans <= #1 1'b0;
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neg_trans <= #1 1'b0;
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t2ex_r <= #1 1'b1;
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t2ex_r <= #1 1'b1;
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Line 232... |
end
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end
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end
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end
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//
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//
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (rst) begin
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if (resetn == 1'b0) begin
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tc2_event <= #1 1'b0;
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tc2_event <= #1 1'b0;
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t2_r <= #1 1'b0;
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t2_r <= #1 1'b0;
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end else if (t2) begin
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end else if (t2) begin
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tc2_event <= #1 1'b0;
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tc2_event <= #1 1'b0;
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t2_r <= #1 1'b1;
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t2_r <= #1 1'b1;
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