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Subversion Repositories oms8051mini

[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_top.v] - Diff between revs 20 and 25

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Rev 20	Rev 25
Line 15...	Line 15...
`//// - Simon Teran, simont@opencores.org ////`	`//// - Simon Teran, simont@opencores.org ////`
`//// - Dinesh Annayya, dinesha@opencores.org ////`	`//// - Dinesh Annayya, dinesha@opencores.org ////`
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//// v0.0 - Dinesh A, 8th Dec 2016`	`//// v0.0 - Dinesh A, 8th Dec 2016`
`//// 1. External ROM Interface Removed`	`//// 1. External ROM Interface Removed`
	`//// v0.1 - Dinesh A, 5th Jan 2017`
	`//// 1. Active edge of reset changed from High to Low`
`//// ////`	`//// ////`
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//// ////`	`//// ////`
`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`	`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
`//// ////`	`//// ////`
Line 111...	Line 113...
`//`	`//`


`include "top_defines.v"	`include "top_defines.v"

`module oc8051_top (wb_rst_i, wb_clk_i,`	`module oc8051_top (resetn, wb_clk_i,`

`//interface to data ram`	`//interface to data ram`
`wbd_dat_i,`	`wbd_dat_i,`
`wbd_dat_o,`	`wbd_dat_o,`
`wbd_adr_o,`	`wbd_adr_o,`
Line 179...	Line 181...
`ea_in`	`ea_in`
`);`	`);`



`input wb_rst_i, // reset input`	`input resetn, // reset input`
`wb_clk_i, // clock input`	`wb_clk_i, // clock input`
`int0_i, // interrupt 0`	`int0_i, // interrupt 0`
`int1_i, // interrupt 1`	`int1_i, // interrupt 1`
`ea_in, // external access`	`ea_in, // external access`
`wbd_ack_i, // data acknowalge`	`wbd_ack_i, // data acknowalge`
Line 348...	Line 350...

`//`	`//`
`// decoder`	`// decoder`
`oc8051_decoder u_decoder(`	`oc8051_decoder u_decoder(`
`.clk (wb_clk_i ),`	`.clk (wb_clk_i ),`
`.rst (wb_rst_i ),`	`.resetn (resetn ),`
`.op_in (op1_n ),`	`.op_in (op1_n ),`
`.op1_c (op1_cur ),`	`.op1_c (op1_cur ),`
`.ram_rd_sel_o (ram_rd_sel ),`	`.ram_rd_sel_o (ram_rd_sel ),`
`.ram_wr_sel_o (ram_wr_sel ),`	`.ram_wr_sel_o (ram_wr_sel ),`
`.bit_addr (bit_addr ),`	`.bit_addr (bit_addr ),`
Line 381...	Line 383...

`wire [7:0] sub_result;`	`wire [7:0] sub_result;`
`//`	`//`
`//alu`	`//alu`
`oc8051_alu u_alu(`	`oc8051_alu u_alu(`
`.rst (wb_rst_i ),`	`.resetn (resetn ),`
`.clk (wb_clk_i ),`	`.clk (wb_clk_i ),`
`.op_code (alu_op ),`	`.op_code (alu_op ),`
`.src1 (src1 ),`	`.src1 (src1 ),`
`.src2 (src2 ),`	`.src2 (src2 ),`
`.src3 (src3 ),`	`.src3 (src3 ),`
Line 403...	Line 405...

`//`	`//`
`//data ram`	`//data ram`
`oc8051_ram_top u_ram_top(`	`oc8051_ram_top u_ram_top(`
`.clk (wb_clk_i ),`	`.clk (wb_clk_i ),`
`.rst (wb_rst_i ),`	`.resetn (resetn ),`
`.rd_addr (rd_addr ),`	`.rd_addr (rd_addr ),`
`.rd_data (ram_data ),`	`.rd_data (ram_data ),`
`.wr_addr (wr_addr ),`	`.wr_addr (wr_addr ),`
`.bit_addr (bit_addr_o ),`	`.bit_addr (bit_addr_o ),`
`.wr_data (wr_dat ),`	`.wr_data (wr_dat ),`
Line 427...	Line 429...

`//`	`//`

`oc8051_alu_src_sel u_alu_src_sel(`	`oc8051_alu_src_sel u_alu_src_sel(`
`.clk (wb_clk_i ),`	`.clk (wb_clk_i ),`
`.rst (wb_rst_i ),`	`.resetn (resetn ),`
`.rd (rd ),`	`.rd (rd ),`

`.sel1 (src_sel1 ),`	`.sel1 (src_sel1 ),`
`.sel2 (src_sel2 ),`	`.sel2 (src_sel2 ),`
`.sel3 (src_sel3 ),`	`.sel3 (src_sel3 ),`
Line 464...	Line 466...

`//`	`//`
`//program rom`	`//program rom`
`ifdef OC8051_ROM	`ifdef OC8051_ROM
`oc8051_rom u_rom(`	`oc8051_rom u_rom(`
`.rst (wb_rst_i ),`	`.resetn (resetn ),`
`.clk (wb_clk_i ),`	`.clk (wb_clk_i ),`
`.ea_int (ea_int ),`	`.ea_int (ea_int ),`
`.addr (iadr_o ),`	`.addr (iadr_o ),`
`.data_o (idat_onchip )`	`.data_o (idat_onchip )`
`);`	`);`
Line 499...	Line 501...
`);`	`);`
`//`	`//`
`//`	`//`
`oc8051_indi_addr u_indi_addr (`	`oc8051_indi_addr u_indi_addr (`
`.clk (wb_clk_i ),`	`.clk (wb_clk_i ),`
`.rst (wb_rst_i ),`	`.resetn (resetn ),`
`.wr_addr (wr_addr ),`	`.wr_addr (wr_addr ),`
`.data_in (wr_dat ),`	`.data_in (wr_dat ),`
`.wr (wr_o ),`	`.wr (wr_o ),`
`.wr_bit (bit_addr_o ),`	`.wr_bit (bit_addr_o ),`
`.ri_out (ri ),`	`.ri_out (ri ),`
Line 515...	Line 517...

`//`	`//`
`//`	`//`
`oc8051_memory_interface u_memory_interface(`	`oc8051_memory_interface u_memory_interface(`
`.clk (wb_clk_i ),`	`.clk (wb_clk_i ),`
`.rst (wb_rst_i ),`	`.resetn (resetn ),`
`// internal ram`	`// internal ram`
`.wr_i (wr ),`	`.wr_i (wr ),`
`.wr_o (wr_o ),`	`.wr_o (wr_o ),`
`.wr_bit_i (bit_addr ),`	`.wr_bit_i (bit_addr ),`
`.wr_bit_o (bit_addr_o ),`	`.wr_bit_o (bit_addr_o ),`
Line 592...	Line 594...

`//`	`//`
`//`	`//`

`oc8051_sfr u_sfr(`	`oc8051_sfr u_sfr(`
`.rst (wb_rst_i ),`	`.resetn (resetn ),`
`.clk (wb_clk_i ),`	`.clk (wb_clk_i ),`
`.adr0 (rd_addr[7:0] ),`	`.adr0 (rd_addr[7:0] ),`
`.adr1 (wr_addr[7:0] ),`	`.adr1 (wr_addr[7:0] ),`
`.dat0 (sfr_out ),`	`.dat0 (sfr_out ),`
`.dat1 (wr_dat ),`	`.dat1 (wr_dat ),`
Line 710...	Line 712...
`reg [7:0] stack_pop;`	`reg [7:0] stack_pop;`
`reg [7:0] pushpop_cnt;`	`reg [7:0] pushpop_cnt;`

`// Assumption, Both Write and Read access will not be`	`// Assumption, Both Write and Read access will not be`
`// possbile in single clock cycle`	`// possbile in single clock cycle`
`always @(posedge wb_clk_i or posedge wb_rst_i)`	`always @(posedge wb_clk_i or negedge resetn)`
`begin`	`begin`
`if(wb_rst_i) begin`	`if(resetn == 1'b0) begin`
`pushpop_cnt = 0;`	`pushpop_cnt = 0;`
`end`	`end`
`else begin`	`else begin`
if(ram_wr_sel==`OC8051_RWS_SP) begin	if(ram_wr_sel==`OC8051_RWS_SP) begin
`StackMem.push_back(wr_dat);`	`StackMem.push_back(wr_dat);`

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[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_top.v] - Diff between revs 20 and 25