| Line 46... |
Line 46... |
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
|
|
|
|
module clkgen (
|
module clkgen (
|
reset_n ,
|
aresetn ,
|
fastsim_mode ,
|
fastsim_mode ,
|
mastermode ,
|
mastermode ,
|
xtal_clk ,
|
xtal_clk ,
|
clkout ,
|
clkout ,
|
gen_resetn ,
|
gen_resetn ,
|
| Line 59... |
Line 59... |
uart_ref_clk
|
uart_ref_clk
|
);
|
);
|
|
|
|
|
|
|
input reset_n ; // Async reset signal
|
input aresetn ; // Async reset signal
|
input fastsim_mode ; // fast sim mode = 1
|
input fastsim_mode ; // fast sim mode = 1
|
input mastermode ; // 1 : Risc master mode
|
input mastermode ; // 1 : Risc master mode
|
input xtal_clk ; // Xtal clock-25Mhx
|
input xtal_clk ; // Xtal clock-25Mhx
|
output clkout ; // clock output, 250Mhz
|
output clkout ; // clock output, 250Mhz
|
output gen_resetn ; // internally generated reset
|
output gen_resetn ; // internally generated reset
|
| Line 89... |
Line 89... |
/***********************************************
|
/***********************************************
|
Alternal PLL pr-programmed for xtal: 25Mhz , clkout 250Mhz
|
Alternal PLL pr-programmed for xtal: 25Mhz , clkout 250Mhz
|
*********************************************************/
|
*********************************************************/
|
/*******************
|
/*******************
|
altera_stargate_pll u_pll (
|
altera_stargate_pll u_pll (
|
. areset (!reset_n ),
|
. areset (!aresetn ),
|
. inclk0 (xtal_clk),
|
. inclk0 (xtal_clk),
|
. c0 (pllout),
|
. c0 (pllout),
|
. locked ()
|
. locked ()
|
);
|
);
|
*************************/
|
*************************/
|
| Line 103... |
Line 103... |
//---------------------------------------------
|
//---------------------------------------------
|
//
|
//
|
// 100us use 25.000 Mhz clock, counter = 2500(0x9C4)
|
// 100us use 25.000 Mhz clock, counter = 2500(0x9C4)
|
|
|
//--------------------------------------------
|
//--------------------------------------------
|
always @(posedge xtal_clk or negedge reset_n)
|
always @(posedge xtal_clk or negedge aresetn)
|
begin // {
|
begin // {
|
if (!reset_n)
|
if (!aresetn)
|
begin // {
|
begin // {
|
pll_count <= 12'h9C4;
|
pll_count <= 12'h9C4;
|
end // }
|
end // }
|
else if (configure_st)
|
else if (configure_st)
|
begin // {
|
begin // {
|
| Line 124... |
Line 124... |
|
|
/************************************************
|
/************************************************
|
PLL Timer Counter
|
PLL Timer Counter
|
************************************************/
|
************************************************/
|
|
|
always @(posedge xtal_clk or negedge reset_n)
|
always @(posedge xtal_clk or negedge aresetn)
|
begin
|
begin
|
if (!reset_n)
|
if (!aresetn)
|
pll_done <= 0;
|
pll_done <= 0;
|
else if (pll_count == 16'h0)
|
else if (pll_count == 16'h0)
|
pll_done <= 1;
|
pll_done <= 1;
|
else if (configure_st)
|
else if (configure_st)
|
pll_done <= 0;
|
pll_done <= 0;
|
| Line 138... |
Line 138... |
|
|
|
|
/************************************************
|
/************************************************
|
internally generated reset
|
internally generated reset
|
************************************************/
|
************************************************/
|
always @(posedge xtal_clk or negedge reset_n )
|
always @(posedge xtal_clk or negedge aresetn )
|
begin
|
begin
|
if (!reset_n) begin
|
if (!aresetn) begin
|
gen_resetn <= 0;
|
gen_resetn <= 0;
|
risc_resetn <= 0;
|
risc_resetn <= 0;
|
end else if(run_st ) begin
|
end else if(run_st ) begin
|
gen_resetn <= 1;
|
gen_resetn <= 1;
|
risc_resetn <= 1;
|
risc_resetn <= 1;
|
| Line 174... |
Line 174... |
assign configure_st = (clkgen_ps == `CONFIGURE);
|
assign configure_st = (clkgen_ps == `CONFIGURE);
|
assign wait_pll_st = (clkgen_ps == `WAIT_PLL);
|
assign wait_pll_st = (clkgen_ps == `WAIT_PLL);
|
assign run_st = (clkgen_ps == `RUN);
|
assign run_st = (clkgen_ps == `RUN);
|
assign slave_run_st = (clkgen_ps == `SLAVE_RUN);
|
assign slave_run_st = (clkgen_ps == `SLAVE_RUN);
|
|
|
always @(posedge xtal_clk or negedge reset_n)
|
always @(posedge xtal_clk or negedge aresetn)
|
begin
|
begin
|
if (!reset_n) begin
|
if (!aresetn) begin
|
clkgen_ps <= `HARD_RESET;
|
clkgen_ps <= `HARD_RESET;
|
end
|
end
|
else begin
|
else begin
|
case (clkgen_ps)
|
case (clkgen_ps)
|
`HARD_RESET:
|
`HARD_RESET:
|
