| Line 1... |
Line 1... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// OMS 8051 Dgital core Module ////
|
//// OMS 8051 Digital core Module ////
|
//// ////
|
//// ////
|
//// This file is part of the OMS 8051 cores project ////
|
//// This file is part of the OMS 8051 cores project ////
|
//// http://www.opencores.org/cores/oms8051mini/ ////
|
//// http://www.opencores.org/cores/oms8051mini/ ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
| Line 21... |
Line 21... |
// 1. MAC related logic are remved
|
// 1. MAC related logic are remved
|
// v0.1 - Dinesh A, 1st Dec 2016
|
// v0.1 - Dinesh A, 1st Dec 2016
|
// 1. RAM and ROM are internally connected to interconnect
|
// 1. RAM and ROM are internally connected to interconnect
|
// 2. Memory Map Change
|
// 2. Memory Map Change
|
// 3. Remove the External ROM Option & Enabled Internal ROM
|
// 3. Remove the External ROM Option & Enabled Internal ROM
|
|
// v0.2 - Dinesh A, 9st Dec 2016
|
|
// 1. Bus interface is changed from 32 bit to 8 bit
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
| Line 67... |
Line 69... |
ext_reg_cs ,
|
ext_reg_cs ,
|
ext_reg_tid ,
|
ext_reg_tid ,
|
ext_reg_wr ,
|
ext_reg_wr ,
|
ext_reg_addr ,
|
ext_reg_addr ,
|
ext_reg_wdata ,
|
ext_reg_wdata ,
|
ext_reg_be ,
|
|
|
|
// Outputs
|
// Outputs
|
ext_reg_rdata ,
|
ext_reg_rdata ,
|
ext_reg_ack ,
|
ext_reg_ack ,
|
|
|
| Line 115... |
Line 116... |
//---------------------------------
|
//---------------------------------
|
input ext_reg_cs ;
|
input ext_reg_cs ;
|
input ext_reg_wr ;
|
input ext_reg_wr ;
|
input [3:0] ext_reg_tid ;
|
input [3:0] ext_reg_tid ;
|
input [14:0] ext_reg_addr ;
|
input [14:0] ext_reg_addr ;
|
input [31:0] ext_reg_wdata ;
|
input [7:0] ext_reg_wdata ;
|
input [3:0] ext_reg_be ;
|
|
|
|
// Outputs
|
// Outputs
|
output [31:0] ext_reg_rdata ;
|
output [7:0] ext_reg_rdata ;
|
output ext_reg_ack ;
|
output ext_reg_ack ;
|
|
|
|
|
|
|
//----------------------------------------
|
//----------------------------------------
|
| Line 147... |
Line 147... |
//---------------------------------------
|
//---------------------------------------
|
wire [15:0] wb_xram_adr ; // data-ram address
|
wire [15:0] wb_xram_adr ; // data-ram address
|
wire wb_xram_ack ; // data-ram acknowlage
|
wire wb_xram_ack ; // data-ram acknowlage
|
wire wb_xram_err ; // data-ram error
|
wire wb_xram_err ; // data-ram error
|
wire wb_xram_wr ; // data-ram error
|
wire wb_xram_wr ; // data-ram error
|
wire [3:0] wb_xram_be ; // Byte enable
|
wire [7:0] wb_xram_rdata ; // ram data input
|
wire [31:0] wb_xram_rdata ; // ram data input
|
wire [7:0] wb_xram_wdata ; // ram data input
|
wire [31:0] wb_xram_wdata ; // ram data input
|
|
|
|
wire wb_xram_stb ; // data-ram strobe
|
wire wb_xram_stb ; // data-ram strobe
|
wire wb_xram_cyc ; // data-ram cycle
|
wire wb_xram_cyc ; // data-ram cycle
|
|
|
|
|
//---------------------------------------------
|
//---------------------------------------------
|
// 8051 Instruction ROM interface
|
// 8051 Instruction ROM interface
|
//---------------------------------------------
|
//---------------------------------------------
|
wire [15:0] wbi_risc_adr;
|
wire [15:0] wbi_risc_adr;
|
wire [31:0] wbi_risc_rdata;
|
wire [7:0] wbi_risc_rdata;
|
|
|
|
|
//-----------------------------
|
//-----------------------------
|
// wire Decleration
|
// wire Decleration
|
//-----------------------------
|
//-----------------------------
|
| Line 177... |
Line 176... |
wire [7:0] wbd_risc_rdata ;
|
wire [7:0] wbd_risc_rdata ;
|
wire [7:0] wbd_risc_wdata ;
|
wire [7:0] wbd_risc_wdata ;
|
|
|
|
|
wire [14:0] reg_uart_addr ;
|
wire [14:0] reg_uart_addr ;
|
wire [31:0] reg_uart_wdata ;
|
wire [7:0] reg_uart_wdata ;
|
wire [3:0] reg_uart_be ;
|
wire [7:0] reg_uart_rdata ;
|
wire [31:0] reg_uart_rdata ;
|
|
wire reg_uart_ack ;
|
wire reg_uart_ack ;
|
|
|
wire [14:0] reg_spi_addr ;
|
wire [14:0] reg_spi_addr ;
|
wire [31:0] reg_spi_wdata ;
|
wire [7:0] reg_spi_wdata ;
|
wire [3:0] reg_spi_be ;
|
wire [7:0] reg_spi_rdata ;
|
wire [31:0] reg_spi_rdata ;
|
|
wire reg_spi_ack ;
|
wire reg_spi_ack ;
|
|
|
wire [3:0] wb_xrom_be ;
|
|
|
|
wire [7:0] p0 ;
|
wire [7:0] p0 ;
|
wire [7:0] p1 ;
|
wire [7:0] p1 ;
|
wire [7:0] p2 ;
|
wire [7:0] p2 ;
|
wire [7:0] p3 ;
|
wire [7:0] p3 ;
|
|
|
|
|
wire [31:0] reg_rdata = (reg_uart_ack) ? reg_uart_rdata :
|
wire [7:0] reg_rdata = (reg_uart_ack) ? reg_uart_rdata :
|
(reg_spi_ack) ? reg_spi_rdata : 'h0;
|
(reg_spi_ack) ? reg_spi_rdata : 'h0;
|
|
|
wire reg_ack = reg_uart_ack | reg_spi_ack;
|
wire reg_ack = reg_uart_ack | reg_spi_ack;
|
|
|
|
|
assign reset_out_n = gen_resetn;
|
assign reset_out_n = gen_resetn;
|
|
|
|
|
assign wb_xram_adr[15] = 0;
|
assign wb_xram_adr[15] = 0;
|
assign wb_xram_adr[1:0] = 2'b00;
|
|
|
|
assign reg_uart_addr[1:0] = 2'b0;
|
|
assign reg_spi_addr[1:0] = 2'b0;
|
|
//-------------------------------------------
|
//-------------------------------------------
|
// clock-gen instantiation
|
// clock-gen instantiation
|
//-------------------------------------------
|
//-------------------------------------------
|
clkgen u_clkgen (
|
clkgen u_clkgen (
|
. reset_n (reset_n ),
|
. reset_n (reset_n ),
|
| Line 228... |
Line 220... |
|
|
);
|
);
|
|
|
|
|
|
|
wire [31:0] wb_master2_rdata;
|
wire [7:0] wb_master2_rdata;
|
|
|
wire [3:0] wb_master2_be = (wbd_risc_adr[1:0] == 2'b00) ? 4'b0001:
|
assign wbd_risc_rdata = wb_master2_rdata[7:0];
|
(wbd_risc_adr[1:0] == 2'b01) ? 4'b0010:
|
|
(wbd_risc_adr[1:0] == 2'b10) ? 4'b0100: 4'b1000;
|
|
|
|
assign wbd_risc_rdata = (wbd_risc_adr[1:0] == 2'b00) ? wb_master2_rdata[7:0]:
|
|
(wbd_risc_adr[1:0] == 2'b01) ? wb_master2_rdata[15:8]:
|
|
(wbd_risc_adr[1:0] == 2'b10) ? wb_master2_rdata[23:16]:
|
|
wb_master2_rdata[31:24];
|
|
|
|
//------------------------------
|
//------------------------------
|
// 8051 Data Memory Map
|
// 8051 Data Memory Map
|
// 0x0000 to 0x7FFFF - Data Memory
|
// 0x0000 to 0x7FFFF - Data Memory
|
// 0x8000 to 0x8FFF - SPI
|
// 0x8000 to 0x8FFF - SPI
|
| Line 257... |
Line 242... |
(wbd_risc_adr[15:12] == 4'b1000 ) ? 4'b0001 :
|
(wbd_risc_adr[15:12] == 4'b1000 ) ? 4'b0001 :
|
(wbd_risc_adr[15:12] == 4'b1001 ) ? 4'b0010 : 4'b0000;
|
(wbd_risc_adr[15:12] == 4'b1001 ) ? 4'b0010 : 4'b0000;
|
|
|
wb_crossbar #(.WB_MASTER(3),
|
wb_crossbar #(.WB_MASTER(3),
|
.WB_SLAVE(3),
|
.WB_SLAVE(3),
|
.D_WD(32),
|
.D_WD(8),
|
.BE_WD(4),
|
.BE_WD(1),
|
.ADR_WD(13),
|
.ADR_WD(15),
|
.TAR_WD(4))
|
.TAR_WD(4))
|
u_wb_crossbar (
|
u_wb_crossbar (
|
|
|
.rst_n (gen_resetn ),
|
.rst_n (gen_resetn ),
|
.clk (app_clk ),
|
.clk (app_clk ),
|
| Line 272... |
Line 257... |
// Master Interface Signal
|
// Master Interface Signal
|
.wbd_taddr_master ({4'b0000,
|
.wbd_taddr_master ({4'b0000,
|
wbd_tar_id,
|
wbd_tar_id,
|
ext_reg_tid }),
|
ext_reg_tid }),
|
|
|
.wbd_din_master ({32'h0 ,
|
.wbd_din_master ({8'h0 ,
|
{wbd_risc_wdata[7:0],
|
|
wbd_risc_wdata[7:0],
|
|
wbd_risc_wdata[7:0],
|
wbd_risc_wdata[7:0],
|
wbd_risc_wdata[7:0]},
|
|
ext_reg_wdata }
|
ext_reg_wdata }
|
),
|
),
|
|
|
.wbd_dout_master ({wbi_risc_rdata,
|
.wbd_dout_master ({wbi_risc_rdata,
|
wb_master2_rdata,
|
wb_master2_rdata,
|
ext_reg_rdata}),
|
ext_reg_rdata}),
|
|
|
.wbd_adr_master ({wbi_risc_adr[12:0],
|
.wbd_adr_master ({wbi_risc_adr[14:0],
|
wbd_risc_adr[14:2],
|
wbd_risc_adr[14:0],
|
ext_reg_addr[14:2]}),
|
ext_reg_addr[14:0]}),
|
|
|
.wbd_be_master ({4'b1111,
|
.wbd_be_master ({1'b1,1'b1,1'b1}),
|
wb_master2_be,
|
|
ext_reg_be }
|
|
),
|
|
|
|
.wbd_we_master ({1'b0,wbd_risc_we,ext_reg_wr } ),
|
.wbd_we_master ({1'b0,wbd_risc_we,ext_reg_wr } ),
|
|
|
.wbd_ack_master ({wbi_risc_ack,
|
.wbd_ack_master ({wbi_risc_ack,
|
wbd_risc_ack,
|
wbd_risc_ack,
|
| Line 318... |
Line 297... |
wb_xram_wdata
|
wb_xram_wdata
|
}),
|
}),
|
|
|
.wbd_dout_slave ({reg_uart_rdata,
|
.wbd_dout_slave ({reg_uart_rdata,
|
reg_spi_rdata,
|
reg_spi_rdata,
|
{wb_xram_rdata}
|
wb_xram_rdata
|
}),
|
}),
|
|
|
.wbd_adr_slave ({reg_uart_addr[14:2],
|
.wbd_adr_slave ({reg_uart_addr[14:0],
|
reg_spi_addr[14:2],
|
reg_spi_addr[14:0],
|
wb_xram_adr[14:2]}
|
wb_xram_adr[14:0]}
|
),
|
),
|
|
|
.wbd_be_slave ({reg_uart_be,
|
.wbd_be_slave (),
|
reg_spi_be,
|
|
wb_xram_be }
|
|
),
|
|
|
|
.wbd_we_slave ({reg_uart_wr,
|
.wbd_we_slave ({reg_uart_wr,
|
reg_spi_wr,
|
reg_spi_wr,
|
wb_xram_wr
|
wb_xram_wr
|
}),
|
}),
|
| Line 366... |
Line 342... |
|
|
|
|
// Reg Bus Interface Signal
|
// Reg Bus Interface Signal
|
. reg_cs (reg_uart_cs ),
|
. reg_cs (reg_uart_cs ),
|
. reg_wr (reg_uart_wr ),
|
. reg_wr (reg_uart_wr ),
|
. reg_addr (reg_uart_addr[5:2] ),
|
. reg_addr (reg_uart_addr[3:0] ),
|
. reg_wdata (reg_uart_wdata ),
|
. reg_wdata (reg_uart_wdata ),
|
. reg_be (reg_uart_be ),
|
. reg_be (1'b1 ),
|
|
|
// Outputs
|
// Outputs
|
. reg_rdata (reg_uart_rdata ),
|
. reg_rdata (reg_uart_rdata ),
|
. reg_ack (reg_uart_ack ),
|
. reg_ack (reg_uart_ack ),
|
|
|
| Line 396... |
Line 372... |
. reset_n (gen_resetn ),
|
. reset_n (gen_resetn ),
|
|
|
// Reg Bus Interface Signal
|
// Reg Bus Interface Signal
|
. reg_cs (reg_spi_cs ),
|
. reg_cs (reg_spi_cs ),
|
. reg_wr (reg_spi_wr ),
|
. reg_wr (reg_spi_wr ),
|
. reg_addr (reg_spi_addr[5:2] ),
|
. reg_addr (reg_spi_addr[3:0] ),
|
. reg_wdata (reg_spi_wdata ),
|
. reg_wdata (reg_spi_wdata ),
|
. reg_be (reg_spi_be ),
|
. reg_be (1'b1 ),
|
|
|
// Outputs
|
// Outputs
|
. reg_rdata (reg_spi_rdata ),
|
. reg_rdata (reg_spi_rdata ),
|
. reg_ack (reg_spi_ack ),
|
. reg_ack (reg_spi_ack ),
|
|
|
| Line 418... |
Line 394... |
|
|
oc8051_top u_8051_core (
|
oc8051_top u_8051_core (
|
. wb_rst_i (risc_reset ),
|
. wb_rst_i (risc_reset ),
|
. wb_clk_i (app_clk ),
|
. wb_clk_i (app_clk ),
|
|
|
//interface to instruction rom
|
|
. wbi_adr_o (wbi_risc_adr ),
|
|
. wbi_dat_i (wbi_risc_rdata ),
|
|
. wbi_stb_o (wbi_risc_stb ),
|
|
. wbi_ack_i (wbi_risc_ack ),
|
|
. wbi_cyc_o (wbi_risc_cyc ),
|
|
. wbi_err_i (wbi_risc_err ),
|
|
|
|
//interface to data ram
|
//interface to data ram
|
. wbd_dat_i (wbd_risc_rdata ),
|
. wbd_dat_i (wbd_risc_rdata ),
|
. wbd_dat_o (wbd_risc_wdata ),
|
. wbd_dat_o (wbd_risc_wdata ),
|
. wbd_adr_o (wbd_risc_adr ),
|
. wbd_adr_o (wbd_risc_adr ),
|
. wbd_we_o (wbd_risc_we ),
|
. wbd_we_o (wbd_risc_we ),
|
| Line 500... |
Line 468... |
//
|
//
|
oc8051_xram oc8051_xram1 (
|
oc8051_xram oc8051_xram1 (
|
.clk (app_clk ),
|
.clk (app_clk ),
|
.rst (!reset_n ),
|
.rst (!reset_n ),
|
.wr (wb_xram_wr ),
|
.wr (wb_xram_wr ),
|
.be (wb_xram_be ),
|
|
.addr (wb_xram_adr ),
|
.addr (wb_xram_adr ),
|
.data_in (wb_xram_wdata ),
|
.data_in (wb_xram_wdata ),
|
.data_out (wb_xram_rdata ),
|
.data_out (wb_xram_rdata ),
|
.ack (wb_xram_ack ),
|
.ack (wb_xram_ack ),
|
.stb (wb_xram_stb )
|
.stb (wb_xram_stb )
|
