| Line 154... |
Line 154... |
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wire wb_xram_stb ; // data-ram strobe
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wire wb_xram_stb ; // data-ram strobe
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wire wb_xram_cyc ; // data-ram cycle
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wire wb_xram_cyc ; // data-ram cycle
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//---------------------------------------------
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// 8051 Instruction ROM interface
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//---------------------------------------------
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wire [15:0] wbi_risc_adr;
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wire [7:0] wbi_risc_rdata;
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//-----------------------------
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//-----------------------------
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// wire Decleration
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// wire Decleration
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//-----------------------------
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//-----------------------------
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wire gen_resetn ;
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wire gen_resetn ;
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| Line 240... |
Line 234... |
//
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//
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wire [3:0] wbd_tar_id = (wbd_risc_adr[15] == 1'b0 ) ? 4'b0000 :
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wire [3:0] wbd_tar_id = (wbd_risc_adr[15] == 1'b0 ) ? 4'b0000 :
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(wbd_risc_adr[15:12] == 4'b1000 ) ? 4'b0001 :
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(wbd_risc_adr[15:12] == 4'b1000 ) ? 4'b0001 :
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(wbd_risc_adr[15:12] == 4'b1001 ) ? 4'b0010 : 4'b0000;
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(wbd_risc_adr[15:12] == 4'b1001 ) ? 4'b0010 : 4'b0000;
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wb_crossbar #(.WB_MASTER(3),
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wb_crossbar #(.WB_MASTER(2),
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.WB_SLAVE(3),
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.WB_SLAVE(3),
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.D_WD(8),
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.D_WD(8),
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.BE_WD(1),
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.BE_WD(1),
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.ADR_WD(15),
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.ADR_WD(15),
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.TAR_WD(4))
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.TAR_WD(4))
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| Line 253... |
Line 247... |
.rst_n (gen_resetn ),
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.rst_n (gen_resetn ),
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.clk (app_clk ),
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.clk (app_clk ),
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// Master Interface Signal
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// Master Interface Signal
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.wbd_taddr_master ({4'b0000,
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.wbd_taddr_master ({ wbd_tar_id,
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wbd_tar_id,
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ext_reg_tid }),
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ext_reg_tid }),
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.wbd_din_master ({8'h0 ,
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.wbd_din_master ({wbd_risc_wdata[7:0],
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wbd_risc_wdata[7:0],
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ext_reg_wdata }
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ext_reg_wdata }
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),
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),
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.wbd_dout_master ({wbi_risc_rdata,
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.wbd_dout_master ({wb_master2_rdata,
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wb_master2_rdata,
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ext_reg_rdata}),
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ext_reg_rdata}),
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.wbd_adr_master ({wbi_risc_adr[14:0],
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.wbd_adr_master ({wbd_risc_adr[14:0],
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wbd_risc_adr[14:0],
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ext_reg_addr[14:0]}),
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ext_reg_addr[14:0]}),
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.wbd_be_master ({1'b1,1'b1,1'b1}),
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.wbd_be_master ({1'b1,1'b1}),
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.wbd_we_master ({1'b0,wbd_risc_we,ext_reg_wr } ),
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.wbd_we_master ({wbd_risc_we,ext_reg_wr } ),
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.wbd_ack_master ({wbi_risc_ack,
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.wbd_ack_master ({wbd_risc_ack,
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wbd_risc_ack,
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ext_reg_ack } ),
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ext_reg_ack } ),
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.wbd_stb_master ({1'b0,
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.wbd_stb_master ({wbd_risc_stb,
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wbd_risc_stb,
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ext_reg_cs} ),
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ext_reg_cs} ),
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.wbd_cyc_master ({1'b0,
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.wbd_cyc_master ({wbd_risc_stb|wbd_risc_ack,
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wbd_risc_stb|wbd_risc_ack,
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ext_reg_cs|ext_reg_ack }),
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ext_reg_cs|ext_reg_ack }),
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.wbd_err_master (),
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.wbd_err_master (),
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.wbd_rty_master (),
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.wbd_rty_master (),
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