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[/] [oms8051mini/] [trunk/] [rtl/] [core/] [digital_core.v] - Diff between revs 14 and 19

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Rev 14 Rev 19
Line 23... Line 23... 
//          1. RAM and ROM are internally connected to interconnect
 
//          1. RAM and ROM are internally connected to interconnect
 
//          2. Memory Map Change
 
//          2. Memory Map Change
 
//          3. Remove the External ROM Option & Enabled Internal ROM
 
//          3. Remove the External ROM Option & Enabled Internal ROM
 
//     v0.2 - Dinesh A, 9st Dec 2016
 
//     v0.2 - Dinesh A, 9st Dec 2016
 
//          1. Bus interface is changed from 32 bit to 8 bit
 
//          1. Bus interface is changed from 32 bit to 8 bit
 
 
 
//     v0.3 - Dinesh A, 21 Dec 2016
 
 
 
//          1. Uart Message Handler is integrated 
 
 
//          2. Message handler is connected as Register Master to 
 
 
//             Inter-connect
 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
////                                                              ////
 
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
 
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
 
////                                                              ////
 
////                                                              ////
 
//// This source file may be used and distributed without         ////
 
//// This source file may be used and distributed without         ////
Line 77... Line 81... 
             ext_reg_ack            ,
 
             ext_reg_ack            ,
 
 
 
 
 
 
 
 
 
 
 
 
 
       // UART Line Interface
 
       // UART Line Interface
 
             si                     ,
 
             uart0_txd              ,
 
             so                     ,
 
             uart0_rxd              ,
 
 
 
 
 
 
 
             uart1_txd              ,
 
 
 
             uart1_rxd              ,
 
 
 
 
 
             spi_sck                ,
 
             spi_sck                ,
 
             spi_so                 ,
 
             spi_so                 ,
 
             spi_si                 ,
 
             spi_si                 ,
 
             spi_cs_n
 
             spi_cs_n
Line 127... Line 133... 
 
 
 
 
 
 
 
 
//----------------------------------------
 
//----------------------------------------
 
// UART Line Interface
 
// UART Line Interface
 
//----------------------------------------
 
//----------------------------------------
 
input            si                     ; // serial in
 
input            uart0_rxd             ; // serial in
 
output           so                     ; // serial out
 
output           uart0_txd             ; // serial out
 
 
 
 
 
 
 
input            uart1_rxd             ; // serial in
 
 
 
output           uart1_txd             ; // serial out
 
 
 
 
 
//----------------------------------------
 
//----------------------------------------
 
// SPI Line Interface
 
// SPI Line Interface
 
//----------------------------------------
 
//----------------------------------------
 
 
 
 
Line 154... Line 163... 
 
 
 
 
wire             wb_xram_stb            ; // data-ram strobe
 
wire             wb_xram_stb            ; // data-ram strobe
 
wire             wb_xram_cyc            ; // data-ram cycle
 
wire             wb_xram_cyc            ; // data-ram cycle
 
 
 
 
 
 
 
 
 
 
 
//----------------------------------------
 
 
 
// Message Controller Reg Master
 
 
 
//---------------------------------------
 
 
 
wire             mh_reg_cs              ;
 
 
 
wire             mh_reg_wr              ;
 
 
 
wire  [3:0]      mh_reg_tid             ;
 
 
 
wire  [15:0]     mh_reg_addr            ;
 
 
 
wire  [7:0]      mh_reg_wdata           ;
 
 
 
 
 
 
 
// Outputs
 
 
 
wire  [7:0]      mh_reg_rdata           ;
 
 
 
wire             mh_reg_ack             ;
 
 
 
 
 
//-----------------------------
 
//-----------------------------
 
// wire Decleration
 
// wire Decleration
 
//-----------------------------
 
//-----------------------------
 
wire             gen_resetn             ;
 
wire             gen_resetn             ;
Line 212... Line 233... 
               . app_clk                (app_clk               ),
 
               . app_clk                (app_clk               ),
 
               . uart_ref_clk           (uart_clk_16x          )
 
               . uart_ref_clk           (uart_clk_16x          )
 
 
 
 
 
              );
 
              );
 
 
 
 
 
 
 
/************* Message Handler **********/
 
 
 
 
 
 
 
msg_handler_top u_msg_hand_top (
 
 
 
              . line_reset_n            (reset_n               ),
 
 
 
              . line_clk                (app_clk               ),
 
 
 
 
 
 
 
      // Towards Register Interface
 
 
 
              . reg_addr                (mh_reg_addr           ),
 
 
 
              . reg_wr                  (mh_reg_wr             ),
 
 
 
              . reg_wdata               (mh_reg_wdata          ),
 
 
 
              . reg_req                 (mh_reg_cs             ),
 
 
 
              . reg_ack                 (mh_reg_ack            ),
 
 
 
              . reg_rdata               (mh_reg_rdata          ),
 
 
 
 
 
 
 
       // Status information
 
 
 
              . frm_error               (                      ),
 
 
 
              . par_error               (                      ),
 
 
 
 
 
 
 
              . baud_clk_16x            (                      ),
 
 
 
 
 
 
 
       // Line Interface
 
 
 
              . rxd                     (uart0_rxd             ),
 
 
 
              . txd                     (uart0_txd             )
 
 
 
 
 
 
 
 
 
 
 
     );
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
/***************************************/
 
wire [7:0] wb_master2_rdata;
 
wire [7:0] wb_master2_rdata;
 
 
 
 
 
assign     wbd_risc_rdata = wb_master2_rdata[7:0];
 
assign     wbd_risc_rdata = wb_master2_rdata[7:0];
 
 
 
 
 
//------------------------------
 
//------------------------------
Line 234... Line 283... 
// 
// 
wire [3:0] wbd_tar_id     = (wbd_risc_adr[15]    == 1'b0 ) ? 4'b0000 :
 
wire [3:0] wbd_tar_id     = (wbd_risc_adr[15]    == 1'b0 ) ? 4'b0000 :
 
                            (wbd_risc_adr[15:12] == 4'b1000 ) ? 4'b0001 :
 
                            (wbd_risc_adr[15:12] == 4'b1000 ) ? 4'b0001 :
 
                            (wbd_risc_adr[15:12] == 4'b1001 ) ? 4'b0010 : 4'b0000;
 
                            (wbd_risc_adr[15:12] == 4'b1001 ) ? 4'b0010 : 4'b0000;
 
 
 
 
 
wb_crossbar #(.WB_MASTER(2),
 
wire [3:0] mh_tar_id     = (mh_reg_addr[15]    == 1'b0 ) ? 4'b0000 :
 
 
 
                           (mh_reg_addr[15:12] == 4'b1000 ) ? 4'b0001 :
 
 
 
                           (mh_reg_addr[15:12] == 4'b1001 ) ? 4'b0010 : 4'b0000;
 
 
 
 
 
 
 
wb_crossbar #(.WB_MASTER(3),
 
              .WB_SLAVE(3),
 
              .WB_SLAVE(3),
 
              .D_WD(8),
 
              .D_WD(8),
 
              .BE_WD(1),
 
              .BE_WD(1),
 
              .ADR_WD(15),
 
              .ADR_WD(15),
 
              .TAR_WD(4))
 
              .TAR_WD(4))
Line 247... Line 300... 
              .rst_n                    (gen_resetn           ),
 
              .rst_n                    (gen_resetn           ),
 
              .clk                      (app_clk              ),
 
              .clk                      (app_clk              ),
 
 
 
 
 
 
 
 
 
    // Master Interface Signal
 
    // Master Interface Signal
 
              .wbd_taddr_master         ({ wbd_tar_id,
 
              .wbd_taddr_master         ({mh_tar_id,
 
 
 
                                          wbd_tar_id,
 
                                          ext_reg_tid }),
 
                                          ext_reg_tid }),
 
 
 
 
 
              .wbd_din_master           ({wbd_risc_wdata[7:0],
 
              .wbd_din_master           ({mh_reg_wdata,
 
 
 
                                          wbd_risc_wdata[7:0],
 
                                          ext_reg_wdata }
 
                                          ext_reg_wdata }
 
                                         ),
 
                                         ),
 
 
 
 
 
              .wbd_dout_master          ({wb_master2_rdata,
 
              .wbd_dout_master          ({mh_reg_rdata,
 
 
 
                                          wb_master2_rdata,
 
                                          ext_reg_rdata}),
 
                                          ext_reg_rdata}),
 
 
 
 
 
              .wbd_adr_master           ({wbd_risc_adr[14:0],
 
              .wbd_adr_master           ({mh_reg_addr[14:0],
 
 
 
                                          wbd_risc_adr[14:0],
 
                                          ext_reg_addr[14:0]}),
 
                                          ext_reg_addr[14:0]}),
 
 
 
 
 
              .wbd_be_master            ({1'b1,1'b1}),
 
              .wbd_be_master            ({1'b1,1'b1,1'b1}),
 
 
 
 
 
              .wbd_we_master            ({wbd_risc_we,ext_reg_wr }   ),
 
              .wbd_we_master            ({mh_reg_wr,
 
 
 
                                          wbd_risc_we,
 
 
 
                                          ext_reg_wr }   ),
 
 
 
 
 
              .wbd_ack_master           ({wbd_risc_ack,
 
              .wbd_ack_master           ({mh_reg_ack,
 
 
 
                                          wbd_risc_ack,
 
                                          ext_reg_ack } ),
 
                                          ext_reg_ack } ),
 
 
 
 
 
              .wbd_stb_master           ({wbd_risc_stb,
 
              .wbd_stb_master           ({mh_reg_cs,
 
 
 
                                          wbd_risc_stb,
 
                                          ext_reg_cs} ),
 
                                          ext_reg_cs} ),
 
 
 
 
 
              .wbd_cyc_master           ({wbd_risc_stb|wbd_risc_ack,
 
              .wbd_cyc_master           ({mh_reg_cs| mh_reg_ack,
 
 
 
                                          wbd_risc_stb|wbd_risc_ack,
 
                                          ext_reg_cs|ext_reg_ack }),
 
                                          ext_reg_cs|ext_reg_ack }),
 
 
 
 
 
              .wbd_err_master           (),
 
              .wbd_err_master           (),
 
              .wbd_rty_master           (),
 
              .wbd_rty_master           (),
 
 
 
 
Line 340... Line 402... 
          . reg_ack                     (reg_uart_ack          ),
 
          . reg_ack                     (reg_uart_ack          ),
 
 
 
 
 
 
 
 
 
 
 
 
 
       // Line Interface
 
       // Line Interface
 
          . si                          (si                    ),
 
          . si                          (uart1_rxd             ),
 
          . so                          (so                    )
 
          . so                          (uart1_txd             )
 
 
 
 
 
     );
 
     );
 
 
 
 
 
 
 
 
 
//--------------------------------
 
//--------------------------------

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