| Line 20... |
Line 20... |
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
// v0.0 - Dinesh A, 6th Jan 2017
|
// v0.0 - Dinesh A, 6th Jan 2017
|
// 1. Initail version picked from
|
// 1. Initail version picked from
|
// http://www.opencores.org/projects/i2c/
|
// http://www.opencores.org/projects/i2c/
|
//
|
// v0.1 - Dinesh A, 19th Jan 2017
|
|
// 1. Lint warning clean up
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
| Line 139... |
Line 140... |
//
|
//
|
|
|
// whenever the slave is not ready it can delay the cycle by pulling SCL low
|
// whenever the slave is not ready it can delay the cycle by pulling SCL low
|
// delay scl_oen
|
// delay scl_oen
|
always @(posedge clk)
|
always @(posedge clk)
|
dscl_oen <= #1 scl_oen;
|
dscl_oen <= scl_oen;
|
|
|
// slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low
|
// slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low
|
// slave_wait remains asserted until the slave releases SCL
|
// slave_wait remains asserted until the slave releases SCL
|
always @(posedge clk or negedge aresetn)
|
always @(posedge clk or negedge aresetn)
|
if (!aresetn) slave_wait <= 1'b0;
|
if (!aresetn) slave_wait <= 1'b0;
|
| Line 156... |
Line 157... |
|
|
// generate clk enable signal
|
// generate clk enable signal
|
always @(posedge clk or negedge aresetn)
|
always @(posedge clk or negedge aresetn)
|
if (~aresetn)
|
if (~aresetn)
|
begin
|
begin
|
cnt <= #1 16'h0;
|
cnt <= 16'h0;
|
clk_en <= #1 1'b1;
|
clk_en <= 1'b1;
|
end
|
end
|
else if (!sresetn || ~|cnt || !ena || scl_sync)
|
else if (!sresetn || ~|cnt || !ena || scl_sync)
|
begin
|
begin
|
cnt <= #1 clk_cnt;
|
cnt <= clk_cnt;
|
clk_en <= #1 1'b1;
|
clk_en <= 1'b1;
|
end
|
end
|
else if (slave_wait)
|
else if (slave_wait)
|
begin
|
begin
|
cnt <= #1 cnt;
|
cnt <= cnt;
|
clk_en <= #1 1'b0;
|
clk_en <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
cnt <= #1 cnt - 16'h1;
|
cnt <= cnt - 16'h1;
|
clk_en <= #1 1'b0;
|
clk_en <= 1'b0;
|
end
|
end
|
|
|
|
|
// generate bus status controller
|
// generate bus status controller
|
|
|
// capture SDA and SCL
|
// capture SDA and SCL
|
// reduce metastability risk
|
// reduce metastability risk
|
always @(posedge clk or negedge aresetn)
|
always @(posedge clk or negedge aresetn)
|
if (!aresetn)
|
if (!aresetn)
|
begin
|
begin
|
cSCL <= #1 2'b00;
|
cSCL <= 2'b00;
|
cSDA <= #1 2'b00;
|
cSDA <= 2'b00;
|
end
|
end
|
else if (!sresetn)
|
else if (!sresetn)
|
begin
|
begin
|
cSCL <= #1 2'b00;
|
cSCL <= 2'b00;
|
cSDA <= #1 2'b00;
|
cSDA <= 2'b00;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
cSCL <= {cSCL[0],scl_i};
|
cSCL <= {cSCL[0],scl_i};
|
cSDA <= {cSDA[0],sda_i};
|
cSDA <= {cSDA[0],sda_i};
|
| Line 228... |
Line 229... |
|
|
// generate filtered SCL and SDA signals
|
// generate filtered SCL and SDA signals
|
always @(posedge clk or negedge aresetn)
|
always @(posedge clk or negedge aresetn)
|
if (~aresetn)
|
if (~aresetn)
|
begin
|
begin
|
sSCL <= #1 1'b1;
|
sSCL <= 1'b1;
|
sSDA <= #1 1'b1;
|
sSDA <= 1'b1;
|
|
|
dSCL <= #1 1'b1;
|
dSCL <= 1'b1;
|
dSDA <= #1 1'b1;
|
dSDA <= 1'b1;
|
end
|
end
|
else if (!sresetn)
|
else if (!sresetn)
|
begin
|
begin
|
sSCL <= #1 1'b1;
|
sSCL <= 1'b1;
|
sSDA <= #1 1'b1;
|
sSDA <= 1'b1;
|
|
|
dSCL <= #1 1'b1;
|
dSCL <= 1'b1;
|
dSDA <= #1 1'b1;
|
dSDA <= 1'b1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
sSCL <= #1 &fSCL[2:1] | &fSCL[1:0] | (fSCL[2] & fSCL[0]);
|
sSCL <= &fSCL[2:1] | &fSCL[1:0] | (fSCL[2] & fSCL[0]);
|
sSDA <= #1 &fSDA[2:1] | &fSDA[1:0] | (fSDA[2] & fSDA[0]);
|
sSDA <= &fSDA[2:1] | &fSDA[1:0] | (fSDA[2] & fSDA[0]);
|
|
|
dSCL <= #1 sSCL;
|
dSCL <= sSCL;
|
dSDA <= #1 sSDA;
|
dSDA <= sSDA;
|
end
|
end
|
|
|
// detect start condition => detect falling edge on SDA while SCL is high
|
// detect start condition => detect falling edge on SDA while SCL is high
|
// detect stop condition => detect rising edge on SDA while SCL is high
|
// detect stop condition => detect rising edge on SDA while SCL is high
|
reg sta_condition;
|
reg sta_condition;
|
reg sto_condition;
|
reg sto_condition;
|
always @(posedge clk or negedge aresetn)
|
always @(posedge clk or negedge aresetn)
|
if (~aresetn)
|
if (~aresetn)
|
begin
|
begin
|
sta_condition <= #1 1'b0;
|
sta_condition <= 1'b0;
|
sto_condition <= #1 1'b0;
|
sto_condition <= 1'b0;
|
end
|
end
|
else if (!sresetn)
|
else if (!sresetn)
|
begin
|
begin
|
sta_condition <= #1 1'b0;
|
sta_condition <= 1'b0;
|
sto_condition <= #1 1'b0;
|
sto_condition <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
sta_condition <= #1 ~sSDA & dSDA & sSCL;
|
sta_condition <= ~sSDA & dSDA & sSCL;
|
sto_condition <= #1 sSDA & ~dSDA & sSCL;
|
sto_condition <= sSDA & ~dSDA & sSCL;
|
end
|
end
|
|
|
|
|
// generate i2c bus busy signal
|
// generate i2c bus busy signal
|
always @(posedge clk or negedge aresetn)
|
always @(posedge clk or negedge aresetn)
|
if (!aresetn) busy <= #1 1'b0;
|
if (!aresetn) busy <= 1'b0;
|
else if (!sresetn ) busy <= #1 1'b0;
|
else if (!sresetn ) busy <= 1'b0;
|
else busy <= #1 (sta_condition | busy) & ~sto_condition;
|
else busy <= (sta_condition | busy) & ~sto_condition;
|
|
|
|
|
// generate arbitration lost signal
|
// generate arbitration lost signal
|
// aribitration lost when:
|
// aribitration lost when:
|
// 1) master drives SDA high, but the i2c bus is low
|
// 1) master drives SDA high, but the i2c bus is low
|
// 2) stop detected while not requested
|
// 2) stop detected while not requested
|
reg cmd_stop;
|
reg cmd_stop;
|
always @(posedge clk or negedge aresetn)
|
always @(posedge clk or negedge aresetn)
|
if (~aresetn)
|
if (~aresetn)
|
cmd_stop <= #1 1'b0;
|
cmd_stop <= 1'b0;
|
else if (!sresetn)
|
else if (!sresetn)
|
cmd_stop <= #1 1'b0;
|
cmd_stop <= 1'b0;
|
else if (clk_en)
|
else if (clk_en)
|
cmd_stop <= #1 cmd == `I2C_CMD_STOP;
|
cmd_stop <= cmd == `I2C_CMD_STOP;
|
|
|
always @(posedge clk or negedge aresetn)
|
always @(posedge clk or negedge aresetn)
|
if (~aresetn)
|
if (~aresetn)
|
al <= #1 1'b0;
|
al <= 1'b0;
|
else if (!sresetn)
|
else if (!sresetn)
|
al <= #1 1'b0;
|
al <= 1'b0;
|
else
|
else
|
al <= #1 (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop);
|
al <= (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop);
|
|
|
|
|
// generate dout signal (store SDA on rising edge of SCL)
|
// generate dout signal (store SDA on rising edge of SCL)
|
always @(posedge clk)
|
always @(posedge clk)
|
if (sSCL & ~dSCL) dout <= #1 sSDA;
|
if (sSCL & ~dSCL) dout <= sSDA;
|
|
|
|
|
// generate statemachine
|
// generate statemachine
|
|
|
// nxt_state decoder
|
// nxt_state decoder
|
| Line 332... |
Line 333... |
parameter [17:0] wr_d = 18'b1_0000_0000_0000_0000;
|
parameter [17:0] wr_d = 18'b1_0000_0000_0000_0000;
|
|
|
always @(posedge clk or negedge aresetn)
|
always @(posedge clk or negedge aresetn)
|
if (!aresetn)
|
if (!aresetn)
|
begin
|
begin
|
c_state <= #1 idle;
|
c_state <= idle;
|
cmd_ack <= #1 1'b0;
|
cmd_ack <= 1'b0;
|
scl_oen <= #1 1'b1;
|
scl_oen <= 1'b1;
|
sda_oen <= #1 1'b1;
|
sda_oen <= 1'b1;
|
sda_chk <= #1 1'b0;
|
sda_chk <= 1'b0;
|
end
|
end
|
else if (!sresetn | al)
|
else if (!sresetn | al)
|
begin
|
begin
|
c_state <= #1 idle;
|
c_state <= idle;
|
cmd_ack <= #1 1'b0;
|
cmd_ack <= 1'b0;
|
scl_oen <= #1 1'b1;
|
scl_oen <= 1'b1;
|
sda_oen <= #1 1'b1;
|
sda_oen <= 1'b1;
|
sda_chk <= #1 1'b0;
|
sda_chk <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
cmd_ack <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
|
cmd_ack <= 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
|
|
|
if (clk_en)
|
if (clk_en)
|
case (c_state) // synopsys full_case parallel_case
|
case (c_state) // synopsys full_case parallel_case
|
// idle state
|
// idle state
|
idle:
|
idle:
|
begin
|
begin
|
case (cmd) // synopsys full_case parallel_case
|
case (cmd) // synopsys full_case parallel_case
|
`I2C_CMD_START: c_state <= #1 start_a;
|
`I2C_CMD_START: c_state <= start_a;
|
`I2C_CMD_STOP: c_state <= #1 stop_a;
|
`I2C_CMD_STOP: c_state <= stop_a;
|
`I2C_CMD_WRITE: c_state <= #1 wr_a;
|
`I2C_CMD_WRITE: c_state <= wr_a;
|
`I2C_CMD_READ: c_state <= #1 rd_a;
|
`I2C_CMD_READ: c_state <= rd_a;
|
default: c_state <= #1 idle;
|
default: c_state <= idle;
|
endcase
|
endcase
|
|
|
scl_oen <= #1 scl_oen; // keep SCL in same state
|
scl_oen <= scl_oen; // keep SCL in same state
|
sda_oen <= #1 sda_oen; // keep SDA in same state
|
sda_oen <= sda_oen; // keep SDA in same state
|
sda_chk <= #1 1'b0; // don't check SDA output
|
sda_chk <= 1'b0; // don't check SDA output
|
end
|
end
|
|
|
// start
|
// start
|
start_a:
|
start_a:
|
begin
|
begin
|
c_state <= #1 start_b;
|
c_state <= start_b;
|
scl_oen <= #1 scl_oen; // keep SCL in same state
|
scl_oen <= scl_oen; // keep SCL in same state
|
sda_oen <= #1 1'b1; // set SDA high
|
sda_oen <= 1'b1; // set SDA high
|
sda_chk <= #1 1'b0; // don't check SDA output
|
sda_chk <= 1'b0; // don't check SDA output
|
end
|
end
|
|
|
start_b:
|
start_b:
|
begin
|
begin
|
c_state <= #1 start_c;
|
c_state <= start_c;
|
scl_oen <= #1 1'b1; // set SCL high
|
scl_oen <= 1'b1; // set SCL high
|
sda_oen <= #1 1'b1; // keep SDA high
|
sda_oen <= 1'b1; // keep SDA high
|
sda_chk <= #1 1'b0; // don't check SDA output
|
sda_chk <= 1'b0; // don't check SDA output
|
end
|
end
|
|
|
start_c:
|
start_c:
|
begin
|
begin
|
c_state <= #1 start_d;
|
c_state <= start_d;
|
scl_oen <= #1 1'b1; // keep SCL high
|
scl_oen <= 1'b1; // keep SCL high
|
sda_oen <= #1 1'b0; // set SDA low
|
sda_oen <= 1'b0; // set SDA low
|
sda_chk <= #1 1'b0; // don't check SDA output
|
sda_chk <= 1'b0; // don't check SDA output
|
end
|
end
|
|
|
start_d:
|
start_d:
|
begin
|
begin
|
c_state <= #1 start_e;
|
c_state <= start_e;
|
scl_oen <= #1 1'b1; // keep SCL high
|
scl_oen <= 1'b1; // keep SCL high
|
sda_oen <= #1 1'b0; // keep SDA low
|
sda_oen <= 1'b0; // keep SDA low
|
sda_chk <= #1 1'b0; // don't check SDA output
|
sda_chk <= 1'b0; // don't check SDA output
|
end
|
end
|
|
|
start_e:
|
start_e:
|
begin
|
begin
|
c_state <= #1 idle;
|
c_state <= idle;
|
cmd_ack <= #1 1'b1;
|
cmd_ack <= 1'b1;
|
scl_oen <= #1 1'b0; // set SCL low
|
scl_oen <= 1'b0; // set SCL low
|
sda_oen <= #1 1'b0; // keep SDA low
|
sda_oen <= 1'b0; // keep SDA low
|
sda_chk <= #1 1'b0; // don't check SDA output
|
sda_chk <= 1'b0; // don't check SDA output
|
end
|
end
|
|
|
// stop
|
// stop
|
stop_a:
|
stop_a:
|
begin
|
begin
|
c_state <= #1 stop_b;
|
c_state <= stop_b;
|
scl_oen <= #1 1'b0; // keep SCL low
|
scl_oen <= 1'b0; // keep SCL low
|
sda_oen <= #1 1'b0; // set SDA low
|
sda_oen <= 1'b0; // set SDA low
|
sda_chk <= #1 1'b0; // don't check SDA output
|
sda_chk <= 1'b0; // don't check SDA output
|
end
|
end
|
|
|
stop_b:
|
stop_b:
|
begin
|
begin
|
c_state <= #1 stop_c;
|
c_state <= stop_c;
|
scl_oen <= #1 1'b1; // set SCL high
|
scl_oen <= 1'b1; // set SCL high
|
sda_oen <= #1 1'b0; // keep SDA low
|
sda_oen <= 1'b0; // keep SDA low
|
sda_chk <= #1 1'b0; // don't check SDA output
|
sda_chk <= 1'b0; // don't check SDA output
|
end
|
end
|
|
|
stop_c:
|
stop_c:
|
begin
|
begin
|
c_state <= #1 stop_d;
|
c_state <= stop_d;
|
scl_oen <= #1 1'b1; // keep SCL high
|
scl_oen <= 1'b1; // keep SCL high
|
sda_oen <= #1 1'b0; // keep SDA low
|
sda_oen <= 1'b0; // keep SDA low
|
sda_chk <= #1 1'b0; // don't check SDA output
|
sda_chk <= 1'b0; // don't check SDA output
|
end
|
end
|
|
|
stop_d:
|
stop_d:
|
begin
|
begin
|
c_state <= #1 idle;
|
c_state <= idle;
|
cmd_ack <= #1 1'b1;
|
cmd_ack <= 1'b1;
|
scl_oen <= #1 1'b1; // keep SCL high
|
scl_oen <= 1'b1; // keep SCL high
|
sda_oen <= #1 1'b1; // set SDA high
|
sda_oen <= 1'b1; // set SDA high
|
sda_chk <= #1 1'b0; // don't check SDA output
|
sda_chk <= 1'b0; // don't check SDA output
|
end
|
end
|
|
|
// read
|
// read
|
rd_a:
|
rd_a:
|
begin
|
begin
|
c_state <= #1 rd_b;
|
c_state <= rd_b;
|
scl_oen <= #1 1'b0; // keep SCL low
|
scl_oen <= 1'b0; // keep SCL low
|
sda_oen <= #1 1'b1; // tri-state SDA
|
sda_oen <= 1'b1; // tri-state SDA
|
sda_chk <= #1 1'b0; // don't check SDA output
|
sda_chk <= 1'b0; // don't check SDA output
|
end
|
end
|
|
|
rd_b:
|
rd_b:
|
begin
|
begin
|
c_state <= #1 rd_c;
|
c_state <= rd_c;
|
scl_oen <= #1 1'b1; // set SCL high
|
scl_oen <= 1'b1; // set SCL high
|
sda_oen <= #1 1'b1; // keep SDA tri-stated
|
sda_oen <= 1'b1; // keep SDA tri-stated
|
sda_chk <= #1 1'b0; // don't check SDA output
|
sda_chk <= 1'b0; // don't check SDA output
|
end
|
end
|
|
|
rd_c:
|
rd_c:
|
begin
|
begin
|
c_state <= #1 rd_d;
|
c_state <= rd_d;
|
scl_oen <= #1 1'b1; // keep SCL high
|
scl_oen <= 1'b1; // keep SCL high
|
sda_oen <= #1 1'b1; // keep SDA tri-stated
|
sda_oen <= 1'b1; // keep SDA tri-stated
|
sda_chk <= #1 1'b0; // don't check SDA output
|
sda_chk <= 1'b0; // don't check SDA output
|
end
|
end
|
|
|
rd_d:
|
rd_d:
|
begin
|
begin
|
c_state <= #1 idle;
|
c_state <= idle;
|
cmd_ack <= #1 1'b1;
|
cmd_ack <= 1'b1;
|
scl_oen <= #1 1'b0; // set SCL low
|
scl_oen <= 1'b0; // set SCL low
|
sda_oen <= #1 1'b1; // keep SDA tri-stated
|
sda_oen <= 1'b1; // keep SDA tri-stated
|
sda_chk <= #1 1'b0; // don't check SDA output
|
sda_chk <= 1'b0; // don't check SDA output
|
end
|
end
|
|
|
// write
|
// write
|
wr_a:
|
wr_a:
|
begin
|
begin
|
c_state <= #1 wr_b;
|
c_state <= wr_b;
|
scl_oen <= #1 1'b0; // keep SCL low
|
scl_oen <= 1'b0; // keep SCL low
|
sda_oen <= #1 din; // set SDA
|
sda_oen <= din; // set SDA
|
sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
|
sda_chk <= 1'b0; // don't check SDA output (SCL low)
|
end
|
end
|
|
|
wr_b:
|
wr_b:
|
begin
|
begin
|
c_state <= #1 wr_c;
|
c_state <= wr_c;
|
scl_oen <= #1 1'b1; // set SCL high
|
scl_oen <= 1'b1; // set SCL high
|
sda_oen <= #1 din; // keep SDA
|
sda_oen <= din; // keep SDA
|
sda_chk <= #1 1'b0; // don't check SDA output yet
|
sda_chk <= 1'b0; // don't check SDA output yet
|
// allow some time for SDA and SCL to settle
|
// allow some time for SDA and SCL to settle
|
end
|
end
|
|
|
wr_c:
|
wr_c:
|
begin
|
begin
|
c_state <= #1 wr_d;
|
c_state <= wr_d;
|
scl_oen <= #1 1'b1; // keep SCL high
|
scl_oen <= 1'b1; // keep SCL high
|
sda_oen <= #1 din;
|
sda_oen <= din;
|
sda_chk <= #1 1'b1; // check SDA output
|
sda_chk <= 1'b1; // check SDA output
|
end
|
end
|
|
|
wr_d:
|
wr_d:
|
begin
|
begin
|
c_state <= #1 idle;
|
c_state <= idle;
|
cmd_ack <= #1 1'b1;
|
cmd_ack <= 1'b1;
|
scl_oen <= #1 1'b0; // set SCL low
|
scl_oen <= 1'b0; // set SCL low
|
sda_oen <= #1 din;
|
sda_oen <= din;
|
sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
|
sda_chk <= 1'b0; // don't check SDA output (SCL low)
|
end
|
end
|
|
|
endcase
|
endcase
|
end
|
end
|
|
|
