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[/] [oms8051mini/] [trunk/] [rtl/] [lib/] [wb_crossbar.v] - Diff between revs 2 and 10

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Rev 2 Rev 10
Line 252... Line 252...
reg  [WB_SLAVE-1:0]   slave_busy;  // slave busy flag
reg  [WB_SLAVE-1:0]   slave_busy;  // slave busy flag
reg  [TAR_WD -1:0]     master_mx_id[WB_MASTER-1:0];
reg  [TAR_WD -1:0]     master_mx_id[WB_MASTER-1:0];
reg  [TAR_WD -1:0]     slave_mx_id [WB_SLAVE-1:0];
reg  [TAR_WD -1:0]     slave_mx_id [WB_SLAVE-1:0];
 
 
reg  [TAR_WD-1 :0]     cur_target_id;
reg  [TAR_WD-1 :0]     cur_target_id;
wire  [TAR_WD-1:0]     wbd_taddr_master_t[WB_MASTER:0]; // target address from master 
wire  [TAR_WD-1:0]     wbd_taddr_master_t[WB_MASTER-1:0]; // target address from master 
wire  [D_WD-1:0]       wbd_din_master_t[WB_MASTER-1:0]; // target address from master 
wire  [D_WD-1:0]       wbd_din_master_t[WB_MASTER-1:0]; // target address from master 
reg   [D_WD-1:0]       wbd_dout_master_t[WB_MASTER-1:0]; // target address from master 
reg   [D_WD-1:0]       wbd_dout_master_t[WB_MASTER-1:0]; // target address from master 
wire  [ADR_WD-1:0]     wbd_adr_master_t[WB_MASTER-1:0]; // target address from master 
wire  [ADR_WD-1:0]     wbd_adr_master_t[WB_MASTER-1:0]; // target address from master 
wire  [BE_WD-1:0]      wbd_be_master_t[WB_MASTER-1:0]; // target address from master 
wire  [BE_WD-1:0]      wbd_be_master_t[WB_MASTER-1:0]; // target address from master 
 
 
Line 351... Line 351...
 
 
*********************************************************/
*********************************************************/
 
 
always @(negedge rst_n or posedge clk) begin
always @(negedge rst_n or posedge clk) begin
   if(rst_n == 0) begin
   if(rst_n == 0) begin
      master_busy   = 0;
      master_busy   <= 0;
      slave_busy    = 0;
      slave_busy    <= 0;
      cur_target_id = 0;
   end else begin
 
 
   end
 
   else begin
 
      for(i = 0; i < WB_MASTER; i = i + 1) begin
      for(i = 0; i < WB_MASTER; i = i + 1) begin
         cur_target_id                     = wbd_taddr_master_t[i];
         cur_target_id                     = wbd_taddr_master_t[i];
         if(master_busy[i] == 0) begin
         if(master_busy[i] == 0) begin
            if(wbd_stb_master[i] & slave_busy[cur_target_id] == 0) begin
            if(wbd_stb_master[i] & slave_busy[wbd_taddr_master_t[i]] == 0) begin
               master_mx_id[i] <= cur_target_id;
               master_mx_id[i] <= wbd_taddr_master_t[i];
               slave_mx_id [cur_target_id] = i;
               slave_mx_id [wbd_taddr_master_t[i]] <= i;
               slave_busy[cur_target_id]   = 1;
               slave_busy[wbd_taddr_master_t[i]]   <= 1;
               master_busy[i]              = 1;
               master_busy[i]              <= 1;
               // synopsys translate_off
               // synopsys translate_off
               // $display("%m:%t: Locking Master : %d with Slave : %d",$time,i,cur_target_id);
               // $display("%m:%t: Locking Master : %d with Slave : %d",$time,i,wbd_taddr_master_t[i]);
               // synopsys translate_on
               // synopsys translate_on
            end
            end
         end else if(wbd_cyc_master[i] == 0) begin
         end else if(wbd_cyc_master[i] == 0) begin
            master_busy[i]            = 0;
            if(master_busy[i] == 1) begin
            slave_busy[cur_target_id] = 0;
            // synopsys translate_off
 
            //  $display("%m:%t: Releasing Master : %d with Slave : %d",$time,i,wbd_taddr_master_t[i]);
 
            // synopsys translate_on
 
            end
 
            master_busy[i]            <= 0;
 
            slave_busy[wbd_taddr_master_t[i]] <= 0;
         end
         end
      end
      end
   end
   end
end
end
 
 

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