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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//// Revision : Nov 26, 2016 ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Revision : Nov 26, 2016
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//// v-0.0 - Dinesh.A, Nov 26, 2016
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//// 1. Initial Version
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//// v-0.1 - Dinesh.A, Jan 19, 2017
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//// 1. Lint warning fixes, Seperated resetable and non
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// resetable logic
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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Line 256... |
reg [WB_MASTER-1:0] master_busy; // master busy flag
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reg [WB_MASTER-1:0] master_busy; // master busy flag
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reg [WB_SLAVE-1:0] slave_busy; // slave busy flag
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reg [WB_SLAVE-1:0] slave_busy; // slave busy flag
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reg [TAR_WD -1:0] master_mx_id[WB_MASTER-1:0];
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reg [TAR_WD -1:0] master_mx_id[WB_MASTER-1:0];
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reg [TAR_WD -1:0] slave_mx_id [WB_SLAVE-1:0];
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reg [TAR_WD -1:0] slave_mx_id [WB_SLAVE-1:0];
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reg [TAR_WD-1 :0] cur_target_id;
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wire [TAR_WD-1:0] wbd_taddr_master_t[WB_MASTER-1:0]; // target address from master
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wire [TAR_WD-1:0] wbd_taddr_master_t[WB_MASTER-1:0]; // target address from master
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wire [D_WD-1:0] wbd_din_master_t[WB_MASTER-1:0]; // target address from master
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wire [D_WD-1:0] wbd_din_master_t[WB_MASTER-1:0]; // target address from master
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reg [D_WD-1:0] wbd_dout_master_t[WB_MASTER-1:0]; // target address from master
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reg [D_WD-1:0] wbd_dout_master_t[WB_MASTER-1:0]; // target address from master
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wire [ADR_WD-1:0] wbd_adr_master_t[WB_MASTER-1:0]; // target address from master
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wire [ADR_WD-1:0] wbd_adr_master_t[WB_MASTER-1:0]; // target address from master
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wire [BE_WD-1:0] wbd_be_master_t[WB_MASTER-1:0]; // target address from master
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wire [BE_WD-1:0] wbd_be_master_t[WB_MASTER-1:0]; // target address from master
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Line 273... |
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reg [D_WD-1:0] wbd_din_slave_t[WB_SLAVE-1:0]; // target address from master
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reg [D_WD-1:0] wbd_din_slave_t[WB_SLAVE-1:0]; // target address from master
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reg [ADR_WD-1:0] wbd_adr_slave_t[WB_SLAVE-1:0]; // target address from master
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reg [ADR_WD-1:0] wbd_adr_slave_t[WB_SLAVE-1:0]; // target address from master
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reg [BE_WD-1:0] wbd_be_slave_t[WB_SLAVE-1:0]; // target address from master
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reg [BE_WD-1:0] wbd_be_slave_t[WB_SLAVE-1:0]; // target address from master
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integer i,k,l;
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integer i,k,l,n;
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/**********************************************************
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/**********************************************************
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Re-Arraging the array in seperate two dimensional information
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Re-Arraging the array in seperate two dimensional information
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***********************************************************/
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***********************************************************/
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if(rst_n == 0) begin
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if(rst_n == 0) begin
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master_busy <= 0;
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master_busy <= 0;
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slave_busy <= 0;
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slave_busy <= 0;
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end else begin
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end else begin
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for(i = 0; i < WB_MASTER; i = i + 1) begin
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for(i = 0; i < WB_MASTER; i = i + 1) begin
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cur_target_id = wbd_taddr_master_t[i];
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if(master_busy[i] == 0) begin
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if(master_busy[i] == 0) begin
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if(wbd_stb_master[i] & slave_busy[wbd_taddr_master_t[i]] == 0) begin
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if(wbd_stb_master[i] & slave_busy[wbd_taddr_master_t[i]] == 0) begin
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master_mx_id[i] <= wbd_taddr_master_t[i];
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slave_mx_id [wbd_taddr_master_t[i]] <= i;
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slave_busy[wbd_taddr_master_t[i]] <= 1;
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slave_busy[wbd_taddr_master_t[i]] <= 1;
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master_busy[i] <= 1;
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master_busy[i] <= 1;
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// synopsys translate_off
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// $display("%m:%t: Locking Master : %d with Slave : %d",$time,i,wbd_taddr_master_t[i]);
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// synopsys translate_on
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end
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end
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end else if(wbd_cyc_master[i] == 0) begin
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end else if(wbd_cyc_master[i] == 0) begin
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if(master_busy[i] == 1) begin
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// synopsys translate_off
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// $display("%m:%t: Releasing Master : %d with Slave : %d",$time,i,wbd_taddr_master_t[i]);
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// synopsys translate_on
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end
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master_busy[i] <= 0;
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master_busy[i] <= 0;
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slave_busy[wbd_taddr_master_t[i]] <= 0;
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slave_busy[wbd_taddr_master_t[i]] <= 0;
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end
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end
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end
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end
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end
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end
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end
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end
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// Seperated non resetable two dimensional reg
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always @(posedge clk) begin
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for(n = 0; n < WB_MASTER; n = n + 1) begin
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if(master_busy[n] == 0) begin
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if(wbd_stb_master[n] & slave_busy[wbd_taddr_master_t[n]] == 0) begin
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master_mx_id[n] <= wbd_taddr_master_t[n];
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slave_mx_id [wbd_taddr_master_t[n]] <= n;
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// synopsys translate_off
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// $display("%m:%t: Locking Master : %d with Slave : %d",$time,i,wbd_taddr_master_t[n]);
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// synopsys translate_on
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end
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end else if(wbd_cyc_master[n] == 0) begin
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if(master_busy[n] == 1) begin
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// synopsys translate_off
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// $display("%m:%t: Releasing Master : %d with Slave : %d",$time,i,wbd_taddr_master_t[n]);
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// synopsys translate_on
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end
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end
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end
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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