| Line 36... |
Line 36... |
-- Offset Bitfield Description Read/Write
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-- Offset Bitfield Description Read/Write
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-- 0x00 AAAAAAAA Region Enables 7:0 (RW)
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-- 0x00 AAAAAAAA Region Enables 7:0 (RW)
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-- 0x01 AAAAAAAA Region Enables 15:8 (RW)
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-- 0x01 AAAAAAAA Region Enables 15:8 (RW)
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-- 0x02 AAAAAAAA Region Enables 23:16 (RW)
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-- 0x02 AAAAAAAA Region Enables 23:16 (RW)
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-- 0x03 AAAAAAAA Region Enables 31:24 (RW)
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-- 0x03 AAAAAAAA Region Enables 31:24 (RW)
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-- 0x04 AAAAAAAA Fault Address 7:0 (RW*)
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-- 0x05 AAAAAAAA Fault Address 15:8 (RW*)
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--
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-- Note: Writing to 0x04 or 0x05 will reset the faulting address to 0x0000
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--
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--
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-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 04/16/20 Revision block added
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-- Seth Henry 04/16/20 Revision block added
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-- Seth Henry 05/12/20 Added write protect logic
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-- Seth Henry 05/12/20 Added write protect logic
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-- Seth Henry 10/04/23 Added faulting address register
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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| Line 70... |
Line 75... |
architecture behave of o8_ram_4k is
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architecture behave of o8_ram_4k is
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alias Clock is Open8_Bus.Clock;
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alias Clock is Open8_Bus.Clock;
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alias Reset is Open8_Bus.Reset;
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alias Reset is Open8_Bus.Reset;
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alias ISR_En is Open8_Bus.GP_Flags(EXT_ISR);
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alias ISR_En is Open8_Bus.GP_Flags(EXT_ISR);
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alias Full_Address is Open8_Bus.Address;
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alias Wr_En is Open8_Bus.Wr_En;
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alias Wr_En is Open8_Bus.Wr_En;
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alias Rd_En is Open8_Bus.Rd_En;
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alias Rd_En is Open8_Bus.Rd_En;
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constant WPR_User_Addr : std_logic_vector(15 downto 2)
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constant WPR_User_Addr : std_logic_vector(15 downto 3)
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:= Address_WPR(15 downto 2);
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:= Address_WPR(15 downto 3);
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constant RAM_User_Addr : std_logic_vector(15 downto 12)
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constant RAM_User_Addr : std_logic_vector(15 downto 12)
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:= Address_RAM(15 downto 12);
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:= Address_RAM(15 downto 12);
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alias WPR_Comp_Addr is Open8_Bus.Address(15 downto 2);
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alias WPR_Comp_Addr is Open8_Bus.Address(15 downto 3);
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signal WPR_Addr_Match : std_logic := '0';
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signal WPR_Addr_Match : std_logic := '0';
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alias WPR_Reg_Sel_d is Open8_Bus.Address(1 downto 0);
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alias WPR_Reg_Sel_d is Open8_Bus.Address(2 downto 0);
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signal WPR_Reg_Sel_q : std_logic_vector(1 downto 0) :=
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signal WPR_Reg_Sel_q : std_logic_vector(2 downto 0) :=
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(others => '0');
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(others => '0');
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alias Wr_Data_d is Open8_Bus.Wr_Data;
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alias Wr_Data_d is Open8_Bus.Wr_Data;
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signal WPR_Wr_Data_q : DATA_TYPE := x"00";
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signal WPR_Wr_Data_q : DATA_TYPE := x"00";
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| Line 115... |
Line 121... |
signal RAM_Rd_En_d : std_logic := '0';
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signal RAM_Rd_En_d : std_logic := '0';
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signal RAM_Rd_En_q : std_logic := '0';
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signal RAM_Rd_En_q : std_logic := '0';
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signal RAM_Rd_Data : DATA_TYPE := OPEN8_NULLBUS;
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signal RAM_Rd_Data : DATA_TYPE := OPEN8_NULLBUS;
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signal Write_Fault_d : std_logic := '0';
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signal Write_Fault_d : std_logic := '0';
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signal Write_Fault_q : std_logic := '0';
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signal Current_Addr : ADDRESS_TYPE := x"0000";
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signal Fault_Addr : ADDRESS_TYPE := x"0000";
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alias Fault_Addr_l is Fault_Addr(7 downto 0);
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alias Fault_Addr_h is Fault_Addr(15 downto 8);
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begin
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begin
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Write_Protect_On : if( Write_Protect )generate
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Write_Protect_On : if( Write_Protect )generate
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WPR_Addr_Match <= '1' when WPR_Comp_Addr = WPR_User_Addr else '0';
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WPR_Addr_Match <= '1' when WPR_Comp_Addr = WPR_User_Addr else '0';
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| Line 134... |
Line 145... |
RAM_Rd_En_d <= RAM_Addr_Match and Rd_En;
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RAM_Rd_En_d <= RAM_Addr_Match and Rd_En;
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RAM_Wr_En_d <= RAM_Addr_Match and RAM_Region_Match and Wr_En;
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RAM_Wr_En_d <= RAM_Addr_Match and RAM_Region_Match and Wr_En;
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Write_Fault_d <= RAM_Addr_Match and (not RAM_Region_Match) and Wr_En;
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Write_Fault_d <= RAM_Addr_Match and (not RAM_Region_Match) and Wr_En;
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Write_Fault <= Write_Fault_q;
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RAM_proc: process( Reset, Clock )
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RAM_proc: process( Reset, Clock )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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WPR_Reg_Sel_q <= (others => '0');
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WPR_Reg_Sel_q <= (others => '0');
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| Line 149... |
Line 162... |
Write_Mask <= Default_Mask;
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Write_Mask <= Default_Mask;
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RAM_Rd_En_q <= '0';
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RAM_Rd_En_q <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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Write_Fault <= '0';
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Write_Fault_q <= '0';
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Current_Addr <= x"0000";
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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WPR_Reg_Sel_q <= WPR_Reg_Sel_d;
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WPR_Reg_Sel_q <= WPR_Reg_Sel_d;
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WPR_Wr_En_q <= WPR_Wr_En_d;
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WPR_Wr_En_q <= WPR_Wr_En_d;
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WPR_Wr_Data_q <= Wr_Data_d;
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WPR_Wr_Data_q <= Wr_Data_d;
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if( WPR_Wr_En_q = '1' )then
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if( WPR_Wr_En_q = '1' )then
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case( WPR_Reg_Sel_q )is
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case( WPR_Reg_Sel_q )is
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when "00" =>
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when "000" =>
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Write_Mask_0 <= WPR_Wr_Data_q;
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Write_Mask_0 <= WPR_Wr_Data_q;
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when "01" =>
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when "001" =>
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Write_Mask_1 <= WPR_Wr_Data_q;
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Write_Mask_1 <= WPR_Wr_Data_q;
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when "10" =>
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when "010" =>
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Write_Mask_2 <= WPR_Wr_Data_q;
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Write_Mask_2 <= WPR_Wr_Data_q;
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when "11" =>
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when "011" =>
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Write_Mask_3 <= WPR_Wr_Data_q;
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Write_Mask_3 <= WPR_Wr_Data_q;
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when "100" | "101" =>
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Fault_Addr <= (others => '0');
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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end if;
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end if;
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| Line 179... |
Line 195... |
Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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if( RAM_Rd_En_q = '1' )then
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if( RAM_Rd_En_q = '1' )then
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Rd_Data <= RAM_Rd_Data;
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Rd_Data <= RAM_Rd_Data;
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elsif( WPR_Rd_En_q = '1' )then
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elsif( WPR_Rd_En_q = '1' )then
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case( WPR_Reg_Sel_q )is
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case( WPR_Reg_Sel_q )is
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when "00" =>
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when "000" =>
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Rd_Data <= Write_Mask_0;
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Rd_Data <= Write_Mask_0;
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when "01" =>
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when "001" =>
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Rd_Data <= Write_Mask_1;
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Rd_Data <= Write_Mask_1;
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when "10" =>
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when "010" =>
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Rd_Data <= Write_Mask_2;
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Rd_Data <= Write_Mask_2;
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when "11" =>
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when "011" =>
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Rd_Data <= Write_Mask_3;
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Rd_Data <= Write_Mask_3;
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when "100" =>
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Rd_Data <= Fault_Addr_l;
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when "101" =>
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Rd_Data <= Fault_Addr_h;
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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end if;
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end if;
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Write_Fault <= Write_Fault_d;
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Write_Fault_q <= Write_Fault_d;
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Current_Addr <= Full_Address;
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if( Write_Fault_q = '1' )then
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Fault_Addr <= Current_Addr;
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end if;
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end if;
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end if;
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end process;
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end process;
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end generate;
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end generate;
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