| Line 26... |
Line 26... |
--
|
--
|
-- Register Map:
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-- Register Map:
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-- Offset Bitfield Description Read/Write
|
-- Offset Bitfield Description Read/Write
|
-- 0x00 AAAAAAAA Minor Version (RO)
|
-- 0x00 AAAAAAAA Minor Version (RO)
|
-- 0x01 AAAAAAAA Major Version (RO)
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-- 0x01 AAAAAAAA Major Version (RO)
|
|
-- 0x02 AAAAAAAA SoC Version (RO)
|
|
-- 0x03 AAAAAAAA Hardware Version (RO)
|
--
|
--
|
-- Revision History
|
-- Revision History
|
-- Author Date Change
|
-- Author Date Change
|
------------------ -------- ---------------------------------------------------
|
------------------ -------- ---------------------------------------------------
|
-- Seth Henry 10/21/20 Initial design
|
-- Seth Henry 10/21/20 Initial design
|
| Line 45... |
Line 47... |
|
|
entity o8_version is
|
entity o8_version is
|
generic(
|
generic(
|
Minor_Version : DATA_TYPE := x"00";
|
Minor_Version : DATA_TYPE := x"00";
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Major_Version : DATA_TYPE := x"00";
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Major_Version : DATA_TYPE := x"00";
|
|
SoC_Version : DATA_TYPE := x"00";
|
|
Hardware_Version : DATA_TYPE := x"00";
|
Address : ADDRESS_TYPE
|
Address : ADDRESS_TYPE
|
);
|
);
|
port(
|
port(
|
Open8_Bus : in OPEN8_BUS_TYPE;
|
Open8_Bus : in OPEN8_BUS_TYPE;
|
Rd_Data : out DATA_TYPE
|
Rd_Data : out DATA_TYPE
|
| Line 58... |
Line 62... |
architecture behave of o8_version is
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architecture behave of o8_version is
|
|
|
alias Clock is Open8_Bus.Clock;
|
alias Clock is Open8_Bus.Clock;
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alias Reset is Open8_Bus.Reset;
|
alias Reset is Open8_Bus.Reset;
|
|
|
constant User_Addr : std_logic_vector(15 downto 1)
|
constant User_Addr : std_logic_vector(15 downto 2)
|
:= Address(15 downto 1);
|
:= Address(15 downto 2);
|
alias Comp_Addr is Open8_Bus.Address(15 downto 1);
|
alias Comp_Addr is Open8_Bus.Address(15 downto 2);
|
signal Addr_Match : std_logic;
|
signal Addr_Match : std_logic;
|
|
|
alias Reg_Sel_d is Open8_Bus.Address(0);
|
alias Reg_Sel_d is Open8_Bus.Address(1 downto 0);
|
signal Reg_Sel_q : std_logic := '0';
|
signal Reg_Sel_q : std_logic_vector(1 downto 0) := "00";
|
signal Rd_En_d : std_logic := '0';
|
signal Rd_En_d : std_logic := '0';
|
signal Rd_En_q : std_logic := '0';
|
signal Rd_En_q : std_logic := '0';
|
|
|
begin
|
begin
|
|
|
| Line 76... |
Line 80... |
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
|
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
|
|
|
io_reg: process( Clock, Reset )
|
io_reg: process( Clock, Reset )
|
begin
|
begin
|
if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
Reg_Sel_q <= '0';
|
Reg_Sel_q <= (others => '0');
|
Rd_En_q <= '0';
|
Rd_En_q <= '0';
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
elsif( rising_edge( Clock ) )then
|
elsif( rising_edge( Clock ) )then
|
Reg_Sel_q <= Reg_Sel_d;
|
Reg_Sel_q <= Reg_Sel_d;
|
|
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_En_q <= Rd_En_d;
|
Rd_En_q <= Rd_En_d;
|
|
|
if( Rd_En_q = '1' )then
|
if( Rd_En_q = '1' )then
|
if( Reg_Sel_q = '0')then
|
case( Reg_Sel_q )is
|
|
when "00" =>
|
Rd_Data <= Minor_Version;
|
Rd_Data <= Minor_Version;
|
else
|
when "01" =>
|
Rd_Data <= Major_Version;
|
Rd_Data <= Major_Version;
|
end if;
|
when "10" =>
|
|
Rd_Data <= Soc_Version;
|
|
when "11" =>
|
|
Rd_Data <= Hardware_Version;
|
|
when others =>
|
|
null;
|
|
end case;
|
|
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
end architecture;
|
end architecture;
|
