| Line 198... |
Line 198... |
reg [31:0] rxmem [0:((1<<MAW)-1)];
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reg [31:0] rxmem [0:((1<<MAW)-1)];
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reg [(MAW+1):0] tx_len;
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reg [(MAW+1):0] tx_len;
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`ifdef RX_SYNCHRONOUS_WITH_WB_CLK
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`ifdef RX_SYNCHRONOUS_WITH_WB_CLK
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wire rx_broadcast;
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wire [(MAW+1):0] rx_len;
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wire [(MAW+1):0] rx_len;
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`else
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`else
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(* ASYNC_REG = "TRUE" *) reg rx_broadcast;
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(* ASYNC_REG = "TRUE" *) reg [(MAW+1):0] rx_len;
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(* ASYNC_REG = "TRUE" *) reg [(MAW+1):0] rx_len;
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`endif
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`endif
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reg tx_cmd, tx_cancel;
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reg tx_cmd, tx_cancel;
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`ifdef TX_SYNCHRONOUS_WITH_WB_CLK
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`ifdef TX_SYNCHRONOUS_WITH_WB_CLK
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| Line 301... |
Line 303... |
wire [31:0] w_tx_ctrl;
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wire [31:0] w_tx_ctrl;
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wire [31:0] w_rx_ctrl;
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wire [31:0] w_rx_ctrl;
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wire [3:0] w_maw;
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wire [3:0] w_maw;
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assign w_maw = MAW+2; // Number of bits in the packet length field
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assign w_maw = MAW+2; // Number of bits in the packet length field
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assign w_rx_ctrl = { 4'h0, w_maw, {(24-19){1'b0}}, rx_crcerr, rx_err,
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assign w_rx_ctrl = { 4'h0, w_maw, {(24-20){1'b0}},
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(rx_valid)&&(rx_broadcast)&&(!rx_clear),
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rx_crcerr, rx_err,
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rx_miss, rx_busy, (rx_valid)&&(!rx_clear),
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rx_miss, rx_busy, (rx_valid)&&(!rx_clear),
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{(14-MAW-2){1'b0}}, rx_len };
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{(14-MAW-2){1'b0}}, rx_len };
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assign w_tx_ctrl = { 4'h0, w_maw, {(24-19){1'b0}},
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assign w_tx_ctrl = { 4'h0, w_maw, {(24-19){1'b0}},
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!config_hw_ip_check,
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!config_hw_ip_check,
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| Line 681... |
Line 685... |
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`ifdef RX_SYNCHRONOUS_WITH_WB_CLK
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`ifdef RX_SYNCHRONOUS_WITH_WB_CLK
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assign rx_busy = n_rx_busy;
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assign rx_busy = n_rx_busy;
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assign rx_valid = n_rx_valid;
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assign rx_valid = n_rx_valid;
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assign rx_len = n_rx_len;
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assign rx_len = n_rx_len;
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assign rx_broadcast = n_rx_broadcast;
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`else
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`else
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reg r_rx_busy, r_rx_valid;
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reg r_rx_busy, r_rx_valid;
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always @(posedge i_wb_clk)
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always @(posedge i_wb_clk)
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begin
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begin
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r_rx_valid <= n_rx_valid;
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r_rx_valid <= n_rx_valid;
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| Line 692... |
Line 697... |
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r_rx_busy <= n_rx_busy;
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r_rx_busy <= n_rx_busy;
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rx_busy <= r_rx_busy;
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rx_busy <= r_rx_busy;
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rx_len <= n_rx_len;
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rx_len <= n_rx_len;
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rx_broadcast <= n_rx_broadcast;
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end
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end
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`endif
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`endif
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reg [3:0] rx_err_pipe, rx_miss_pipe, rx_crc_pipe;
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reg [3:0] rx_err_pipe, rx_miss_pipe, rx_crc_pipe;
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