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--! @brief ControlUnit http://en.wikipedia.org/wiki/Control_unit
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--! @brief ControlUnit http://en.wikipedia.org/wiki/Control_unit
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--! @details The control unit receives external instructions or commands which it converts into a sequence of control signals that the control \n
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--! @details The control unit receives external instructions or commands which it converts into a sequence of control signals that the control \n
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--! unit applies to data path to implement a sequence of register-transfer level operations.
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--! unit applies to data path to implement a sequence of register-transfer level operations.
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architecture Behavioral of ControlUnit is
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architecture Behavioral of ControlUnit is
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signal currentCpuState : controlUnitStates;
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signal currentCpuState : controlUnitStates; -- CPU states
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signal nextCpuState : controlUnitStates;
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signal nextCpuState : controlUnitStates; -- CPU states
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signal PC : std_logic_vector(n downto 0);
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signal PC : std_logic_vector(n downto 0); -- Program Counter
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signal IR : std_logic_vector(n downto 0);
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signal IR : std_logic_vector(n downto 0); -- Intruction register
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signal currInstruction : std_logic_vector(n downto 0); -- Current Intruction
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begin
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begin
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-- Next state logic
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-- Next state logic
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process (clk, reset)
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process (clk, reset)
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begin
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begin
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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currentCpuState <= nextCpuState;
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currentCpuState <= nextCpuState;
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end if;
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end if;
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end process;
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end process;
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-- assd
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-- States Fetch, decode, execute from the processor
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process (currentCpuState)
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process (currentCpuState)
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variable cyclesExecute : integer range 0 to 20; -- Cycles to wait while executing instruction
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begin
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begin
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case currentCpuState is
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case currentCpuState is
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-- Initial state left from reset ...
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-- Initial state left from reset ...
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when initial =>
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when initial =>
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cyclesExecute := 0;
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PC <= (others => '0');
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PC <= (others => '0');
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IR <= (others => '0');
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MemoryDataRead <= (others => '0');
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MemoryDataRead <= (others => '0');
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MemoryDataWrite <= (others => '0');
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MemoryDataWrite <= (others => '0');
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MemoryDataAddr <= (others => '0');
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MemoryDataAddr <= (others => '0');
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nextCpuState <= fetch;
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nextCpuState <= fetch;
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MemoryDataAddr <= PC; -- Warning PC is not 1 yet...
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MemoryDataAddr <= PC; -- Warning PC is not 1 yet...
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IR <= MemoryDataInput;
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IR <= MemoryDataInput;
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MemoryDataRead <= '1';
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MemoryDataRead <= '1';
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nextCpuState <= decode;
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nextCpuState <= decode;
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-- Detect with instruction came from memory...
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-- Detect with instruction came from memory, set the number of cycles to execute...
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when decode =>
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when decode =>
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MemoryDataRead <= '0';
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MemoryDataRead <= '0';
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MemoryDataWrite <= '0';
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-- The high attribute points to the highes bit position
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case IR((IR'HIGH) downto (IR'HIGH - 5)) is
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when mov_reg =>
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nextCpuState <= execute;
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cyclesExecute := 2;
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currInstruction <= IR;
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-- Invalid instruction (Now will be ignored, but latter shoud rais a trap
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when others =>
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end case;
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-- Wait while the process that handles the execution works..
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when execute =>
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if cyclesExecute > 1 then
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cyclesExecute := cyclesExecute - 1;
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else
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nextCpuState <= fetch;
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end if;
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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end process;
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end process;
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-- Process that handles the execution of each instruction
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process (currInstruction)
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begin
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end process;
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end Behavioral;
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end Behavioral;
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No newline at end of file
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No newline at end of file
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