OpenCores
URL https://opencores.org/ocsvn/opencpu32/opencpu32/trunk

Subversion Repositories opencpu32

[/] [opencpu32/] [trunk/] [hdl/] [opencpu32/] [ControlUnit.vhd] - Diff between revs 31 and 33

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 31 Rev 33
Line 68... Line 68...
        end process;
        end process;
 
 
        -- Next state logic (Execution states)
        -- Next state logic (Execution states)
        process (clk, currentCpuState)
        process (clk, currentCpuState)
        begin
        begin
                if ( (currentCpuState /= execute) and (currentCpuState /= executing) ) then
                if (reset = '1') then
                        currentExState <= initInstructionExecution;
                        currentExState <= initInstructionExecution;
                elsif rising_edge(clk) then
                elsif rising_edge(clk) then
                        currentExState <= nextExState;
                        currentExState <= nextExState;
                end if;
                end if;
        end process;
        end process;
Line 185... Line 185...
                operand_imm  := IR((IR'HIGH - 10) downto (IR'LOW));                     -- 22 bits imediate value (Max value 4194304)
                operand_imm  := IR((IR'HIGH - 10) downto (IR'LOW));                     -- 22 bits imediate value (Max value 4194304)
 
 
                -- Select the instruction and init it's execution
                -- Select the instruction and init it's execution
                case currentExState is
                case currentExState is
                        when initInstructionExecution =>
                        when initInstructionExecution =>
 
                                nextExState <= waitToExecute;
 
 
 
                        when waitToExecute =>
 
                                if ( (currentCpuState /= execute) and (currentCpuState /= executing) ) then
 
                                        nextExState <= initInstructionExecution;
 
                                else
                                case opcodeIR is
                                case opcodeIR is
                                        -- MOV r2,r1 (See the testDatapath to see how to drive the datapath for this function)
                                        -- MOV r2,r1 (See the testDatapath to see how to drive the datapath for this function)
                                        when mov_reg =>
                                        when mov_reg =>
                                                MuxDp <= muxPos(fromRegFileB);
                                                MuxDp <= muxPos(fromRegFileB);
                                                DpRegFileReadAddrB <= Num2reg(conv_integer(UNSIGNED(operand_reg2)));
                                                DpRegFileReadAddrB <= Num2reg(conv_integer(UNSIGNED(operand_reg2)));
Line 243... Line 249...
                                                nextExState <= writeRegister;
                                                nextExState <= writeRegister;
 
 
                                        when others =>
                                        when others =>
                                                null;
                                                null;
                                end case;
                                end case;
 
                                end if;
 
 
                        -- Write something on the register files
                        -- Write something on the register files
                        when writeRegister =>
                        when writeRegister =>
                                DpRegFileWriteEn <= '1';
                                DpRegFileWriteEn <= '1';
                                nextExState <= releaseWriteRead;
                                nextExState <= releaseWriteRead;
Line 265... Line 272...
                        when releaseWriteRead =>
                        when releaseWriteRead =>
                                DpRegFileReadEnB <= '0';
                                DpRegFileReadEnB <= '0';
                                DpRegFileReadEnA <= '0';
                                DpRegFileReadEnA <= '0';
                                DpRegFileWriteEn <= '0';
                                DpRegFileWriteEn <= '0';
                                outEnDp <= disable;
                                outEnDp <= disable;
 
                                -- Come back to waiting state
 
                                nextExState <= waitToExecute;
 
 
                        when others =>
                        when others =>
                                null;
                                null;
                end case;
                end case;
        end process;
        end process;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.