OpenCores
URL https://opencores.org/ocsvn/opencpu32/opencpu32/trunk

Subversion Repositories opencpu32

[/] [opencpu32/] [trunk/] [hdl/] [opencpu32/] [ControlUnit.vhd] - Diff between revs 47 and 48

Show entire file | Details | Blame | View Log

Rev 47 Rev 48
Line 140... Line 140...
                                -- On the case of jump instructions, it's execution will be handled on this process
                                -- On the case of jump instructions, it's execution will be handled on this process
                                case opcodeIR is
                                case opcodeIR is
 
 
                                        when jmp_val =>
                                        when jmp_val =>
                                                PC      <= "0000000000" & operand_imm;
                                                PC      <= "0000000000" & operand_imm;
 
                                                nextCpuState <= fetch;
 
 
                                        when jmpr_val =>
                                        when jmpr_val =>
                                                PC      <= PC + ("0000000000" & operand_imm);
                                                PC      <= PC + ("0000000000" & operand_imm);
 
                                                nextCpuState <= fetch;
 
 
                                        -- ld r5,20 (Load into r5 register the content of the memory at address 20)
                                        -- ld r5,20 (Load into r5 register the content of the memory at address 20)
                                        when ld_val =>
                                        when ld_val =>
                                                MemoryDataRdAddr <= "0000000000" & operand_imm;
                                                MemoryDataRdAddr <= "0000000000" & operand_imm;
                                                MemoryDataReadEn <= '1';
                                                MemoryDataReadEn <= '1';

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.