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regFileReadAddrA : in generalRegisters; --! General register read address (PortA)
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regFileReadAddrA : in generalRegisters; --! General register read address (PortA)
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regFileReadAddrB : in generalRegisters; --! General register read address (PortB)
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regFileReadAddrB : in generalRegisters; --! General register read address (PortB)
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regFileEnA : in STD_LOGIC; --! Enable RegisterFile PortA
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regFileEnA : in STD_LOGIC; --! Enable RegisterFile PortA
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regFileEnB : in STD_LOGIC; --! Enable RegisterFile PortB
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regFileEnB : in STD_LOGIC; --! Enable RegisterFile PortB
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outputDp : out STD_LOGIC_VECTOR (n downto 0); --! DataPath Output
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outputDp : out STD_LOGIC_VECTOR (n downto 0); --! DataPath Output
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dpFlags : out STD_LOGIC_VECTOR (n downto 0)); --! Alu Flags
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dpFlags : out STD_LOGIC_VECTOR (2 downto 0)); --! Alu Flags
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end DataPath;
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end DataPath;
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--! @brief DataPath http://en.wikipedia.org/wiki/Datapath
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--! @brief DataPath http://en.wikipedia.org/wiki/Datapath
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--! @details This description will also show how to instantiate components(Alu, RegisterFile, Multiplexer) on your design
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--! @details This description will also show how to instantiate components(Alu, RegisterFile, Multiplexer) on your design
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architecture Behavioral of DataPath is
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architecture Behavioral of DataPath is
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COMPONENT Alu
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COMPONENT Alu
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 1
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Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 1
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B : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 2
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B : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 2
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S : out STD_LOGIC_VECTOR (n downto 0); --! Alu Output
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S : out STD_LOGIC_VECTOR (n downto 0); --! Alu Output
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flagsOut : out STD_LOGIC_VECTOR(2 downto 0); --! Flags from current operation
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sel : in aluOps); --! Select operation
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sel : in aluOps); --! Select operation
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END COMPONENT;
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END COMPONENT;
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--! Component declaration to instantiate the testRegisterFile circuit
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--! Component declaration to instantiate the testRegisterFile circuit
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COMPONENT RegisterFile
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COMPONENT RegisterFile
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--! Instantiate the Unit Under Test (Alu) (Doxygen bug if it's not commented!)
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--! Instantiate the Unit Under Test (Alu) (Doxygen bug if it's not commented!)
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uAlu: Alu PORT MAP (
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uAlu: Alu PORT MAP (
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A => muxOutReg,
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A => muxOutReg,
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B => regFilePortB,
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B => regFilePortB,
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S => aluOut,
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S => aluOut,
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flagsOut => dpFlags,
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sel => aluOp
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sel => aluOp
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);
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);
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--! Instantiate the Unit Under Test (RegisterFile) (Doxygen bug if it's not commented!)
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--! Instantiate the Unit Under Test (RegisterFile) (Doxygen bug if it's not commented!)
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uRegisterFile: RegisterFile PORT MAP (
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uRegisterFile: RegisterFile PORT MAP (
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