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--! Use CPU Definitions package
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--! Use CPU Definitions package
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use work.pkgOpenCPU32.all;
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use work.pkgOpenCPU32.all;
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ENTITY testControlUnit IS
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ENTITY testControlUnit IS
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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END testControlUnit;
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END testControlUnit;
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--! @brief ControlUnit Testbench file
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--! @brief ControlUnit Testbench file
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--! @details Exercise the control unit with a assembly program sample
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--! @details Exercise the control unit with a assembly program sample
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--! for more information: http://vhdlguru.blogspot.com/2010/03/how-to-write-testbench.html
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--! for more information: http://vhdlguru.blogspot.com/2010/03/how-to-write-testbench.html
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ARCHITECTURE behavior OF testControlUnit IS
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ARCHITECTURE behavior OF testControlUnit IS
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-- Component Declaration for the Unit Under Test (UUT)
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT ControlUnit
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COMPONENT ControlUnit
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PORT(
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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reset : IN std_logic;
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Port ( reset : in STD_LOGIC;
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clk : IN std_logic;
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clk : in STD_LOGIC; --! Main system clock
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FlagsDp : IN std_logic_vector(7 downto 0);
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FlagsDp : in STD_LOGIC_VECTOR (2 downto 0); --! Flags comming from the Datapath
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DataDp : IN std_logic_vector(7 downto 0);
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DataDp : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from the Datapath
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MuxDp : OUT std_logic_vector(2 downto 0);
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outEnDp : out typeEnDis; --! Enable/Disable datapath output
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ImmDp : OUT std_logic_vector(7 downto 0);
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MuxDp : out STD_LOGIC_VECTOR (2 downto 0); --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)
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DpRegFileWriteAddr : OUT std_logic;
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MuxRegDp : out STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
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DpRegFileWriteEn : OUT std_logic;
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ImmDp : out STD_LOGIC_VECTOR (n downto 0); --! Imediate value passed to the Datapath
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DpRegFileReadAddrA : OUT std_logic;
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DpAluOp : out aluOps; --! Alu operations
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DpRegFileReadAddrB : OUT std_logic;
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DpRegFileWriteAddr : out generalRegisters; --! General register address to write
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DpRegFileReadEnA : OUT std_logic;
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DpRegFileWriteEn : out STD_LOGIC; --! Enable register write
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DpRegFileReadEnB : OUT std_logic;
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DpRegFileReadAddrA : out generalRegisters; --! General register address to read
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MemoryDataInput : IN std_logic_vector(7 downto 0);
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DpRegFileReadAddrB : out generalRegisters; --! General register address to read
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MemoryDataAddr : OUT std_logic_vector(7 downto 0);
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DpRegFileReadEnA : out STD_LOGIC; --! Enable register read (PortA)
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MemoryDataOut : OUT std_logic_vector(7 downto 0)
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DpRegFileReadEnB : out STD_LOGIC; --! Enable register read (PortB)
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);
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MemoryDataReadEn : out std_logic; --! Enable Main memory read
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MemoryDataWriteEn: out std_logic; --! Enable Main memory write
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MemoryDataInput : in STD_LOGIC_VECTOR (n downto 0); --! Incoming data from main memory
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MemoryDataRdAddr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Read address
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MemoryDataWrAddr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Write address
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MemoryDataOut : out STD_LOGIC_VECTOR (n downto 0)); --! Data to write on main memory
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END COMPONENT;
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END COMPONENT;
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--Inputs
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--Inputs
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signal reset : std_logic := '0'; --! Wire to connect Test signal to component
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signal reset : std_logic := '0'; --! Wire to connect Test signal to component
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signal clk : std_logic := '0'; --! Wire to connect Test signal to component
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signal clk : std_logic := '0'; --! Wire to connect Test signal to component
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signal FlagsDp : std_logic_vector(7 downto 0) := (others => '0'); --! Wire to connect Test signal to component
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signal FlagsDp : std_logic_vector(2 downto 0) := (others => '0'); --! Wire to connect Test signal to component
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signal DataDp : std_logic_vector(7 downto 0) := (others => '0'); --! Wire to connect Test signal to component
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signal DataDp : std_logic_vector(n downto 0) := (others => '0'); --! Wire to connect Test signal to component
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signal MemoryDataInput : std_logic_vector(7 downto 0) := (others => '0'); --! Wire to connect Test signal to component
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signal MemoryDataInput : std_logic_vector(n downto 0) := (others => '0'); --! Wire to connect Test signal to component
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--Outputs
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--Outputs
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signal outEnDp : typeEnDis; --! Wire to connect Test signal to component
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signal MuxDp : std_logic_vector(2 downto 0); --! Wire to connect Test signal to component
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signal MuxDp : std_logic_vector(2 downto 0); --! Wire to connect Test signal to component
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signal ImmDp : std_logic_vector(7 downto 0); --! Wire to connect Test signal to component
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signal MuxRegDp : std_logic_vector(1 downto 0); --! Wire to connect Test signal to component
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signal DpRegFileWriteAddr : std_logic; --! Wire to connect Test signal to component
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signal ImmDp : std_logic_vector(n downto 0); --! Wire to connect Test signal to component
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signal DpAluOp : aluOps; --! Wire to connect Test signal to component
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signal DpRegFileWriteAddr : generalRegisters; --! Wire to connect Test signal to component
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signal DpRegFileWriteEn : std_logic; --! Wire to connect Test signal to component
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signal DpRegFileWriteEn : std_logic; --! Wire to connect Test signal to component
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signal DpRegFileReadAddrA : std_logic; --! Wire to connect Test signal to component
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signal DpRegFileReadAddrA : generalRegisters; --! Wire to connect Test signal to component
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signal DpRegFileReadAddrB : std_logic; --! Wire to connect Test signal to component
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signal DpRegFileReadAddrB : generalRegisters; --! Wire to connect Test signal to component
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signal DpRegFileReadEnA : std_logic; --! Wire to connect Test signal to component
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signal DpRegFileReadEnA : std_logic; --! Wire to connect Test signal to component
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signal DpRegFileReadEnB : std_logic; --! Wire to connect Test signal to component
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signal DpRegFileReadEnB : std_logic; --! Wire to connect Test signal to component
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signal MemoryDataAddr : std_logic_vector(7 downto 0); --! Wire to connect Test signal to component
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signal MemoryDataReadEn : std_logic; --! Wire to connect Test signal to component
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signal MemoryDataOut : std_logic_vector(7 downto 0); --! Wire to connect Test signal to component
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signal MemoryDataWriteEn : std_logic; --! Wire to connect Test signal to component
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signal MemoryDataRdAddr : std_logic_vector(n downto 0); --! Wire to connect Test signal to component
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signal MemoryDataWrAddr : std_logic_vector(n downto 0); --! Wire to connect Test signal to component
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signal MemoryDataOut : std_logic_vector(n downto 0); --! Wire to connect Test signal to component
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-- Clock period definitions
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-- Clock period definitions
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constant clk_period : time := 10 ns;
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constant clk_period : time := 10 ns;
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BEGIN
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BEGIN
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Line 81... |
uut: ControlUnit PORT MAP (
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uut: ControlUnit PORT MAP (
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reset => reset,
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reset => reset,
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clk => clk,
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clk => clk,
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FlagsDp => FlagsDp,
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FlagsDp => FlagsDp,
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DataDp => DataDp,
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DataDp => DataDp,
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outEnDp => outEnDp,
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MuxDp => MuxDp,
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MuxDp => MuxDp,
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MuxRegDp => MuxRegDp,
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ImmDp => ImmDp,
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ImmDp => ImmDp,
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DpAluOp => DpAluOp,
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DpRegFileWriteAddr => DpRegFileWriteAddr,
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DpRegFileWriteAddr => DpRegFileWriteAddr,
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DpRegFileWriteEn => DpRegFileWriteEn,
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DpRegFileWriteEn => DpRegFileWriteEn,
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DpRegFileReadAddrA => DpRegFileReadAddrA,
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DpRegFileReadAddrA => DpRegFileReadAddrA,
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DpRegFileReadAddrB => DpRegFileReadAddrB,
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DpRegFileReadAddrB => DpRegFileReadAddrB,
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DpRegFileReadEnA => DpRegFileReadEnA,
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DpRegFileReadEnA => DpRegFileReadEnA,
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DpRegFileReadEnB => DpRegFileReadEnB,
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DpRegFileReadEnB => DpRegFileReadEnB,
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MemoryDataReadEn => MemoryDataReadEn,
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MemoryDataWriteEn => MemoryDataWriteEn,
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MemoryDataInput => MemoryDataInput,
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MemoryDataInput => MemoryDataInput,
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MemoryDataAddr => MemoryDataAddr,
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MemoryDataRdAddr => MemoryDataRdAddr,
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MemoryDataWrAddr => MemoryDataWrAddr,
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MemoryDataOut => MemoryDataOut
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MemoryDataOut => MemoryDataOut
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);
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);
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-- Clock process definitions
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-- Clock process definitions
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clk_process :process
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clk_process :process
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Line 113... |
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-- Stimulus process
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-- Stimulus process
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stim_proc: process
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stim_proc: process
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begin
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begin
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-- hold reset state for 100 ns.
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-- Reset operation
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wait for 100 ns;
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REPORT "RESET" SEVERITY NOTE;
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reset <= '1';
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wait for clk_period*10;
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wait for 2 ns;
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reset <= '0';
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-- insert stimulus here
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wait for 2 ns;
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-- MOV r0,10d ---------------------------------------------------------------------------------
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REPORT "MOV r0,10" SEVERITY NOTE;
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wait for CLK_period;
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wait;
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wait;
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end process;
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end process;
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END;
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END;
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