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[/] [opencpu32/] [trunk/] [hdl/] [opencpu32/] [testControlUnit.vhd] - Diff between revs 35 and 40

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Line 8... Line 8... 
use ieee.std_logic_arith.all;
 
use ieee.std_logic_arith.all;
 
 
 
 
 
--! Use CPU Definitions package
 
--! Use CPU Definitions package
 
use work.pkgOpenCPU32.all;
 
use work.pkgOpenCPU32.all;
 
 
 
 
 
 
 
--! Adding library for File I/O 
 
 
-- More information on this site:
 
 
 
-- http://eesun.free.fr/DOC/vhdlref/refguide/language_overview/test_benches/reading_and_writing_files_with_text_i_o.htm
 
 
 
use std.textio.ALL;
 
 
 
use ieee.std_logic_textio.all;
 
 
 
 
 
ENTITY testControlUnit IS
 
ENTITY testControlUnit IS
 
generic (n : integer := nBits - 1);                                                                     --! Generic value (Used to easily change the size of the Alu on the package)
 
generic (n : integer := nBits - 1);                                                                     --! Generic value (Used to easily change the size of the Alu on the package)
 
END testControlUnit;
 
END testControlUnit;
 
 
 
 
 
--! @brief ControlUnit Testbench file
 
--! @brief ControlUnit Testbench file
Line 112... Line 118... 
   end process;
 
   end process;
 
 
 
 
 
 
 
 
 
   -- Stimulus process
 
   -- Stimulus process
 
   stim_proc: process
 
   stim_proc: process
 
 
 
        variable line_out: Line; -- Line that will be written to a file
 
 
 
        file cmdfile: TEXT;      -- Define the file 'handle'
 
   begin
 
   begin
 
                -- Reset operation
 
                -- Reset operation
 
                REPORT "RESET" SEVERITY NOTE;
 
                REPORT "RESET" SEVERITY NOTE;
 
 
 
                -- Open source file for write...
 
 
 
                FILE_OPEN(cmdfile,"testCode/testCodeBin.dat",WRITE_MODE);
 
                reset <= '1';
 
                reset <= '1';
 
      wait for 2 ns;
 
      wait for 2 ns;
 
                reset <= '0';
 
                reset <= '0';
 
                wait for 2 ns;
 
                wait for 2 ns;
 
 
 
 
Line 127... Line 137... 
                MemoryDataInput <= mov_val & conv_std_logic_vector(reg2Num(r0),4) & conv_std_logic_vector(10, 22);
 
                MemoryDataInput <= mov_val & conv_std_logic_vector(reg2Num(r0),4) & conv_std_logic_vector(10, 22);
 
                wait for CLK_period;    -- Fetch
 
                wait for CLK_period;    -- Fetch
 
                wait for CLK_period;    -- Decode
 
                wait for CLK_period;    -- Decode
 
                wait for CLK_period;    -- Execute
 
                wait for CLK_period;    -- Execute
 
 
 
 
 
 
 
                -- Write the command to a file (This will be usefull for the top Testing later)
 
 
 
                WRITE (line_out, MemoryDataInput);
 
 
 
                WRITELINE (cmdfile, line_out);
 
 
 
 
 
                -- Verify if signals for the datapath are valid
 
                -- Verify if signals for the datapath are valid
 
                assert ImmDp = conv_std_logic_vector(10, nBits) report "Invalid value" severity FAILURE;
 
                assert ImmDp = conv_std_logic_vector(10, nBits) report "Invalid value" severity FAILURE;
 
                assert DpRegFileWriteAddr = r0 report "Invalid value" severity FAILURE;
 
                assert DpRegFileWriteAddr = r0 report "Invalid value" severity FAILURE;
 
      assert DpAluOp = alu_pass report "Invalid value" severity FAILURE;
 
      assert DpAluOp = alu_pass report "Invalid value" severity FAILURE;
 
                assert MuxDp = muxPos(fromImediate) report "Invalid value" severity FAILURE;
 
                assert MuxDp = muxPos(fromImediate) report "Invalid value" severity FAILURE;
Line 155... Line 169... 
                MemoryDataInput <= mov_val & conv_std_logic_vector(reg2Num(r1),4) & conv_std_logic_vector(20, 22);
 
                MemoryDataInput <= mov_val & conv_std_logic_vector(reg2Num(r1),4) & conv_std_logic_vector(20, 22);
 
                wait for CLK_period;    -- Fetch
 
                wait for CLK_period;    -- Fetch
 
                wait for CLK_period;    -- Decode
 
                wait for CLK_period;    -- Decode
 
                wait for CLK_period;    -- Execute
 
                wait for CLK_period;    -- Execute
 
 
 
 
 
 
 
                -- Write the command to a file (This will be usefull for the top Testing later)
 
 
 
                WRITE (line_out, MemoryDataInput);
 
 
 
                WRITELINE (cmdfile, line_out);
 
 
 
 
 
                -- Verify if signals for the datapath are valid
 
                -- Verify if signals for the datapath are valid
 
                assert ImmDp = conv_std_logic_vector(20, nBits) report "Invalid value" severity FAILURE;
 
                assert ImmDp = conv_std_logic_vector(20, nBits) report "Invalid value" severity FAILURE;
 
                assert DpRegFileWriteAddr = r1 report "Invalid value" severity FAILURE;
 
                assert DpRegFileWriteAddr = r1 report "Invalid value" severity FAILURE;
 
      assert DpAluOp = alu_pass report "Invalid value" severity FAILURE;
 
      assert DpAluOp = alu_pass report "Invalid value" severity FAILURE;
 
                assert MuxDp = muxPos(fromImediate) report "Invalid value" severity FAILURE;
 
                assert MuxDp = muxPos(fromImediate) report "Invalid value" severity FAILURE;
Line 183... Line 201... 
                MemoryDataInput <= mov_reg & conv_std_logic_vector(reg2Num(r2),4) & conv_std_logic_vector(reg2Num(r1),4) & "000000000000000000";
 
                MemoryDataInput <= mov_reg & conv_std_logic_vector(reg2Num(r2),4) & conv_std_logic_vector(reg2Num(r1),4) & "000000000000000000";
 
                wait for CLK_period;    -- Fetch
 
                wait for CLK_period;    -- Fetch
 
                wait for CLK_period;    -- Decode
 
                wait for CLK_period;    -- Decode
 
                wait for CLK_period;    -- Execute
 
                wait for CLK_period;    -- Execute
 
 
 
 
 
 
 
                -- Write the command to a file (This will be usefull for the top Testing later)
 
 
 
                WRITE (line_out, MemoryDataInput);
 
 
 
                WRITELINE (cmdfile, line_out);
 
 
 
 
 
                -- Verify if signals for the datapath are valid         
                -- Verify if signals for the datapath are valid         
                assert DpRegFileReadAddrB = r1 report "Invalid value" severity FAILURE;
 
                assert DpRegFileReadAddrB = r1 report "Invalid value" severity FAILURE;
 
                assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;
 
                assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;
 
                assert MuxDp = muxPos(fromRegFileB) report "Invalid value" severity FAILURE;
 
                assert MuxDp = muxPos(fromRegFileB) report "Invalid value" severity FAILURE;
 
                assert DpRegFileReadEnB = '1' report "Invalid value" severity FAILURE;
 
                assert DpRegFileReadEnB = '1' report "Invalid value" severity FAILURE;
Line 210... Line 232... 
                MemoryDataInput <= add_reg & conv_std_logic_vector(reg2Num(r2),4) & conv_std_logic_vector(reg2Num(r0),4) & "000000000000000000";
 
                MemoryDataInput <= add_reg & conv_std_logic_vector(reg2Num(r2),4) & conv_std_logic_vector(reg2Num(r0),4) & "000000000000000000";
 
                wait for CLK_period;    -- Fetch
 
                wait for CLK_period;    -- Fetch
 
                wait for CLK_period;    -- Decode
 
                wait for CLK_period;    -- Decode
 
                wait for CLK_period;    -- Execute
 
                wait for CLK_period;    -- Execute
 
 
 
 
 
 
 
                -- Write the command to a file (This will be usefull for the top Testing later)
 
 
 
                WRITE (line_out, MemoryDataInput);
 
 
 
                WRITELINE (cmdfile, line_out);
 
 
 
 
 
                -- Verify if signals for the datapath are valid         
                -- Verify if signals for the datapath are valid         
                assert DpRegFileReadAddrB = r0 report "Invalid value" severity FAILURE;
 
                assert DpRegFileReadAddrB = r0 report "Invalid value" severity FAILURE;
 
                assert DpRegFileReadAddrA = r2 report "Invalid value" severity FAILURE;
 
                assert DpRegFileReadAddrA = r2 report "Invalid value" severity FAILURE;
 
                assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;
 
                assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;
 
                assert MuxDp = muxPos(fromAlu) report "Invalid value" severity FAILURE;
 
                assert MuxDp = muxPos(fromAlu) report "Invalid value" severity FAILURE;
Line 241... Line 267... 
                MemoryDataInput <= add_val & conv_std_logic_vector(reg2Num(r2),4) & conv_std_logic_vector(2, 22);
 
                MemoryDataInput <= add_val & conv_std_logic_vector(reg2Num(r2),4) & conv_std_logic_vector(2, 22);
 
                wait for CLK_period;    -- Fetch
 
                wait for CLK_period;    -- Fetch
 
                wait for CLK_period;    -- Decode
 
                wait for CLK_period;    -- Decode
 
                wait for CLK_period;    -- Execute
 
                wait for CLK_period;    -- Execute
 
 
 
 
 
 
 
                -- Write the command to a file (This will be usefull for the top Testing later)
 
 
 
                WRITE (line_out, MemoryDataInput);
 
 
 
                WRITELINE (cmdfile, line_out);
 
 
 
 
 
                -- Verify if signals for the datapath are valid         
                -- Verify if signals for the datapath are valid         
                assert ImmDp = conv_std_logic_vector(2, nBits) report "Invalid value" severity FAILURE;
 
                assert ImmDp = conv_std_logic_vector(2, nBits) report "Invalid value" severity FAILURE;
 
                assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;
 
                assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;
 
      assert DpAluOp = alu_sum report "Invalid value" severity FAILURE;
 
      assert DpAluOp = alu_sum report "Invalid value" severity FAILURE;
 
                assert MuxDp = muxPos(fromAlu) report "Invalid value" severity FAILURE;
 
                assert MuxDp = muxPos(fromAlu) report "Invalid value" severity FAILURE;
Line 265... Line 295... 
                assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE;
 
                assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE;
 
                assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
 
                assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
 
                assert outEnDp = disable report "Invalid value" severity FAILURE;
 
                assert outEnDp = disable report "Invalid value" severity FAILURE;
 
                -------------------------------------------------------------------------------------------------
 
                -------------------------------------------------------------------------------------------------
 
 
 
 
 
 
 
      -- Close file
 
 
 
                file_close(cmdfile);
 
      -- Finish simulation
 
      -- Finish simulation
 
                assert false report "NONE. End of simulation." severity failure;
 
                assert false report "NONE. End of simulation." severity failure;
 
                wait;
 
                wait;
 
   end process;
 
   end process;
 
 
 
 

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