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[/] [opencpu32/] [trunk/] [hdl/] [opencpu32/] [testDataPath.vhd] - Diff between revs 27 and 29
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| Rev 27 |
Rev 29 |
| Line 33... |
Line 33... |
regFileReadAddrA : in generalRegisters; --! General register read address (PortA)
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regFileReadAddrA : in generalRegisters; --! General register read address (PortA)
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regFileReadAddrB : in generalRegisters; --! General register read address (PortB)
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regFileReadAddrB : in generalRegisters; --! General register read address (PortB)
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regFileEnA : in STD_LOGIC; --! Enable RegisterFile PortA
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regFileEnA : in STD_LOGIC; --! Enable RegisterFile PortA
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regFileEnB : in STD_LOGIC; --! Enable RegisterFile PortB
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regFileEnB : in STD_LOGIC; --! Enable RegisterFile PortB
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outputDp : out STD_LOGIC_VECTOR (n downto 0); --! DataPath Output
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outputDp : out STD_LOGIC_VECTOR (n downto 0); --! DataPath Output
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dpFlags : out STD_LOGIC_VECTOR (n downto 0)); --! Alu Flags
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dpFlags : out STD_LOGIC_VECTOR (2 downto 0)); --! Alu Flags
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END COMPONENT;
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END COMPONENT;
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--Inputs
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--Inputs
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signal inputMm : std_logic_vector(31 downto 0) := (others => 'U'); --! Wire to connect Test signal to component
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signal inputMm : std_logic_vector(31 downto 0) := (others => 'U'); --! Wire to connect Test signal to component
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| Line 54... |
Line 54... |
signal regFileEnA : std_logic := '0'; --! Wire to connect Test signal to component
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signal regFileEnA : std_logic := '0'; --! Wire to connect Test signal to component
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signal regFileEnB : std_logic := '0'; --! Wire to connect Test signal to component
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signal regFileEnB : std_logic := '0'; --! Wire to connect Test signal to component
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--Outputs
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--Outputs
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signal outputDp : std_logic_vector(31 downto 0); --! Wire to connect Test signal to component
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signal outputDp : std_logic_vector(31 downto 0); --! Wire to connect Test signal to component
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signal dpFlags : std_logic_vector(31 downto 0); --! Wire to connect Test signal to component
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signal dpFlags : std_logic_vector(2 downto 0); --! Wire to connect Test signal to component
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-- Clock period definitions
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-- Clock period definitions
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constant CLK_period : time := 10 ns;
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constant CLK_period : time := 10 ns;
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BEGIN
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BEGIN
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