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module ogfx_gpu_dma (
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module ogfx_gpu_dma (
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// OUTPUTs
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// OUTPUTs
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gpu_exec_done_o, // GPU execution done
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gpu_exec_done_o, // GPU execution done
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gpu_dma_busy_o, // GPU DMA execution on going
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vid_ram_addr_o, // Video-RAM address
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vid_ram_addr_o, // Video-RAM address
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vid_ram_din_o, // Video-RAM data
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vid_ram_din_o, // Video-RAM data
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vid_ram_wen_o, // Video-RAM write strobe (active low)
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vid_ram_wen_o, // Video-RAM write strobe (active low)
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vid_ram_cen_o, // Video-RAM chip enable (active low)
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vid_ram_cen_o, // Video-RAM chip enable (active low)
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);
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);
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// OUTPUTs
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// OUTPUTs
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//=========
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//=========
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output gpu_exec_done_o; // GPU execution done
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output gpu_exec_done_o; // GPU execution done
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output gpu_dma_busy_o; // GPU DMA execution on going
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output [`VRAM_MSB:0] vid_ram_addr_o; // Video-RAM address
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output [`VRAM_MSB:0] vid_ram_addr_o; // Video-RAM address
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output [15:0] vid_ram_din_o; // Video-RAM data
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output [15:0] vid_ram_din_o; // Video-RAM data
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output vid_ram_wen_o; // Video-RAM write strobe (active low)
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output vid_ram_wen_o; // Video-RAM write strobe (active low)
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output vid_ram_cen_o; // Video-RAM chip enable (active low)
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output vid_ram_cen_o; // Video-RAM chip enable (active low)
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// Utility signals
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// Utility signals
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wire dma_init = (dma_state==INIT);
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wire dma_init = (dma_state==INIT);
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wire dma_pixel_done = (dma_state==SKIP) | ((dma_state==DST_READ) & pixel_is_transparent) |
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wire dma_pixel_done = (dma_state==SKIP) | ((dma_state==DST_READ) & pixel_is_transparent) |
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((dma_state==DST_WRITE) & data_ready_nxt ) ;
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((dma_state==DST_WRITE) & data_ready_nxt ) ;
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assign gpu_exec_done_o = (dma_state==IDLE) & ~trig_exec_i;
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assign gpu_exec_done_o = (dma_state==IDLE) & ~trig_exec_i;
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assign gpu_dma_busy_o = (dma_state!=IDLE);
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//=============================================================================
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//=============================================================================
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// 3) COUNT TRANSFERS
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// 3) COUNT TRANSFERS
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//=============================================================================
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//=============================================================================
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