| Line 895... |
Line 895... |
vid_ram1_frame_select <= 2'h0;
|
vid_ram1_frame_select <= 2'h0;
|
end
|
end
|
else if (frame_select_wr)
|
else if (frame_select_wr)
|
begin
|
begin
|
refresh_frame_select <= per_din_i[1:0];
|
refresh_frame_select <= per_din_i[1:0];
|
vid_ram0_frame_select <= per_din_i[5:4];
|
vid_ram0_frame_select <= per_din_i[9:8];
|
vid_ram1_frame_select <= per_din_i[7:6];
|
vid_ram1_frame_select <= per_din_i[13:12];
|
end
|
end
|
|
|
wire [15:0] frame_select = {8'h00, vid_ram1_frame_select, vid_ram0_frame_select, 2'h0, refresh_frame_select};
|
wire [15:0] frame_select = {2'h0, vid_ram1_frame_select, 2'h0, vid_ram0_frame_select, 6'h00, refresh_frame_select};
|
`else
|
`else
|
reg refresh_frame_select;
|
reg refresh_frame_select;
|
reg vid_ram0_frame_select;
|
reg vid_ram0_frame_select;
|
reg vid_ram1_frame_select;
|
reg vid_ram1_frame_select;
|
|
|
| Line 915... |
Line 915... |
vid_ram1_frame_select <= 1'h0;
|
vid_ram1_frame_select <= 1'h0;
|
end
|
end
|
else if (frame_select_wr)
|
else if (frame_select_wr)
|
begin
|
begin
|
refresh_frame_select <= per_din_i[0];
|
refresh_frame_select <= per_din_i[0];
|
vid_ram0_frame_select <= per_din_i[4];
|
vid_ram0_frame_select <= per_din_i[8];
|
vid_ram1_frame_select <= per_din_i[6];
|
vid_ram1_frame_select <= per_din_i[12];
|
end
|
end
|
|
|
wire [15:0] frame_select = {8'h00, 1'h0, vid_ram1_frame_select, 1'h0, vid_ram0_frame_select, 2'h0, 1'h0, refresh_frame_select};
|
wire [15:0] frame_select = {3'h0, vid_ram1_frame_select, 3'h0, vid_ram0_frame_select, 7'h00, refresh_frame_select};
|
`endif
|
`endif
|
`else
|
`else
|
wire [15:0] frame_select = 16'h0000;
|
wire [15:0] frame_select = 16'h0000;
|
`endif
|
`endif
|
|
|
