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URL https://opencores.org/ocsvn/opengfx430/opengfx430/trunk

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[/] [opengfx430/] [trunk/] [core/] [rtl/] [verilog/] [ogfx_reg.v] - Diff between revs 3 and 6

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Rev 3 Rev 6
Line 90... Line 90... 
 
 
 
 
// INPUTs
 
// INPUTs
 
    dbg_freeze_i,                              // Freeze address auto-incr on read
 
    dbg_freeze_i,                              // Freeze address auto-incr on read
 
    gpu_cmd_done_evt_i,                        // GPU command done event
 
    gpu_cmd_done_evt_i,                        // GPU command done event
 
    gpu_cmd_error_evt_i,                       // GPU command error event
 
    gpu_cmd_error_evt_i,                       // GPU command error event
 
 
 
    gpu_dma_busy_i,                            // GPU DMA execution on going
 
    gpu_get_data_i,                            // GPU get next data
 
    gpu_get_data_i,                            // GPU get next data
 
    lt24_status_i,                             // LT24 FSM Status
 
    lt24_status_i,                             // LT24 FSM Status
 
    lt24_start_evt_i,                          // LT24 FSM is starting
 
    lt24_start_evt_i,                          // LT24 FSM is starting
 
    lt24_done_evt_i,                           // LT24 FSM is done
 
    lt24_done_evt_i,                           // LT24 FSM is done
 
    mclk,                                      // Main system clock
 
    mclk,                                      // Main system clock
Line 158... Line 159... 
// INPUTs
 
// INPUTs
 
//=========
 
//=========
 
input                dbg_freeze_i;             // Freeze address auto-incr on read
 
input                dbg_freeze_i;             // Freeze address auto-incr on read
 
input                gpu_cmd_done_evt_i;       // GPU command done event
 
input                gpu_cmd_done_evt_i;       // GPU command done event
 
input                gpu_cmd_error_evt_i;      // GPU command error event
 
input                gpu_cmd_error_evt_i;      // GPU command error event
 
 
 
input                gpu_dma_busy_i;           // GPU DMA execution on going
 
input                gpu_get_data_i;           // GPU get next data
 
input                gpu_get_data_i;           // GPU get next data
 
input          [4:0] lt24_status_i;            // LT24 FSM Status
 
input          [4:0] lt24_status_i;            // LT24 FSM Status
 
input                lt24_start_evt_i;         // LT24 FSM is starting
 
input                lt24_start_evt_i;         // LT24 FSM is starting
 
input                lt24_done_evt_i;          // LT24 FSM is done
 
input                lt24_done_evt_i;          // LT24 FSM is done
 
input                mclk;                     // Main system clock
 
input                mclk;                     // Main system clock
Line 191... Line 193... 
                       GFX_STATUS          = 'h08,
 
                       GFX_STATUS          = 'h08,
 
                       GFX_IRQ             = 'h0A,
 
                       GFX_IRQ             = 'h0A,
 
 
 
 
 
                       DISPLAY_WIDTH       = 'h10,  // Display configuration
 
                       DISPLAY_WIDTH       = 'h10,  // Display configuration
 
                       DISPLAY_HEIGHT      = 'h12,
 
                       DISPLAY_HEIGHT      = 'h12,
 
                       DISPLAY_SIZE_HI     = 'h14,
 
                       DISPLAY_SIZE_LO     = 'h14,
 
                       DISPLAY_SIZE_LO     = 'h16,
 
                       DISPLAY_SIZE_HI     = 'h16,
 
                       DISPLAY_CFG         = 'h18,
 
                       DISPLAY_CFG         = 'h18,
 
 
 
 
 
                       LT24_CFG            = 'h20,  // LT24 configuration and Generic command sending
 
                       LT24_CFG            = 'h20,  // LT24 configuration and Generic command sending
 
                       LT24_REFRESH        = 'h22,
 
                       LT24_REFRESH        = 'h22,
 
                       LT24_REFRESH_SYNC   = 'h24,
 
                       LT24_REFRESH_SYNC   = 'h24,
Line 207... Line 209... 
 
 
 
 
                       LUT_RAM_ADDR        = 'h30,  // LUT Memory Access Gate
 
                       LUT_RAM_ADDR        = 'h30,  // LUT Memory Access Gate
 
                       LUT_RAM_DATA        = 'h32,
 
                       LUT_RAM_DATA        = 'h32,
 
 
 
 
 
                       FRAME_SELECT        = 'h3E,  // Frame pointers and selection
 
                       FRAME_SELECT        = 'h3E,  // Frame pointers and selection
 
                       FRAME0_PTR_HI       = 'h40,
 
                       FRAME0_PTR_LO       = 'h40,
 
                       FRAME0_PTR_LO       = 'h42,
 
                       FRAME0_PTR_HI       = 'h42,
 
                       FRAME1_PTR_HI       = 'h44,
 
                       FRAME1_PTR_LO       = 'h44,
 
                       FRAME1_PTR_LO       = 'h46,
 
                       FRAME1_PTR_HI       = 'h46,
 
                       FRAME2_PTR_HI       = 'h48,
 
                       FRAME2_PTR_LO       = 'h48,
 
                       FRAME2_PTR_LO       = 'h4A,
 
                       FRAME2_PTR_HI       = 'h4A,
 
                       FRAME3_PTR_HI       = 'h4C,
 
                       FRAME3_PTR_LO       = 'h4C,
 
                       FRAME3_PTR_LO       = 'h4E,
 
                       FRAME3_PTR_HI       = 'h4E,
 
 
 
 
 
                       VID_RAM0_CFG        = 'h50,  // First Video Memory Access Gate
 
                       VID_RAM0_CFG        = 'h50,  // First Video Memory Access Gate
 
                       VID_RAM0_WIDTH      = 'h52,
 
                       VID_RAM0_WIDTH      = 'h52,
 
                       VID_RAM0_ADDR_HI    = 'h54,
 
                       VID_RAM0_ADDR_LO    = 'h54,
 
                       VID_RAM0_ADDR_LO    = 'h56,
 
                       VID_RAM0_ADDR_HI    = 'h56,
 
                       VID_RAM0_DATA       = 'h58,
 
                       VID_RAM0_DATA       = 'h58,
 
 
 
 
 
                       VID_RAM1_CFG        = 'h60,  // Second Video Memory Access Gate
 
                       VID_RAM1_CFG        = 'h60,  // Second Video Memory Access Gate
 
                       VID_RAM1_WIDTH      = 'h62,
 
                       VID_RAM1_WIDTH      = 'h62,
 
                       VID_RAM1_ADDR_HI    = 'h64,
 
                       VID_RAM1_ADDR_LO    = 'h64,
 
                       VID_RAM1_ADDR_LO    = 'h66,
 
                       VID_RAM1_ADDR_HI    = 'h66,
 
                       VID_RAM1_DATA       = 'h68,
 
                       VID_RAM1_DATA       = 'h68,
 
 
 
 
 
                       GPU_CMD             = 'h70,  // Graphic Processing Unit
 
                       GPU_CMD_LO          = 'h70,  // Graphic Processing Unit
 
                       GPU_STAT            = 'h72;
 
                       GPU_CMD_HI          = 'h72,
 
 
 
                       GPU_STAT            = 'h74;
 
 
 
 
 
 
 
 
 
// Register one-hot decoder utilities
 
// Register one-hot decoder utilities
 
parameter              DEC_SZ              =  (1 << DEC_WD);
 
parameter              DEC_SZ              =  (1 << DEC_WD);
 
parameter [DEC_SZ-1:0] BASE_REG            =  {{DEC_SZ-1{1'b0}}, 1'b1};
 
parameter [DEC_SZ-1:0] BASE_REG            =  {{DEC_SZ-1{1'b0}}, 1'b1};
Line 243... Line 246... 
                       GFX_STATUS_D        = (BASE_REG << GFX_STATUS        ),
 
                       GFX_STATUS_D        = (BASE_REG << GFX_STATUS        ),
 
                       GFX_IRQ_D           = (BASE_REG << GFX_IRQ           ),
 
                       GFX_IRQ_D           = (BASE_REG << GFX_IRQ           ),
 
 
 
 
 
                       DISPLAY_WIDTH_D     = (BASE_REG << DISPLAY_WIDTH     ),
 
                       DISPLAY_WIDTH_D     = (BASE_REG << DISPLAY_WIDTH     ),
 
                       DISPLAY_HEIGHT_D    = (BASE_REG << DISPLAY_HEIGHT    ),
 
                       DISPLAY_HEIGHT_D    = (BASE_REG << DISPLAY_HEIGHT    ),
 
                       DISPLAY_SIZE_HI_D   = (BASE_REG << DISPLAY_SIZE_HI   ),
 
 
 
                       DISPLAY_SIZE_LO_D   = (BASE_REG << DISPLAY_SIZE_LO   ),
 
                       DISPLAY_SIZE_LO_D   = (BASE_REG << DISPLAY_SIZE_LO   ),
 
 
 
                       DISPLAY_SIZE_HI_D   = (BASE_REG << DISPLAY_SIZE_HI   ),
 
                       DISPLAY_CFG_D       = (BASE_REG << DISPLAY_CFG       ),
 
                       DISPLAY_CFG_D       = (BASE_REG << DISPLAY_CFG       ),
 
 
 
 
 
                       LT24_CFG_D          = (BASE_REG << LT24_CFG          ),
 
                       LT24_CFG_D          = (BASE_REG << LT24_CFG          ),
 
                       LT24_REFRESH_D      = (BASE_REG << LT24_REFRESH      ),
 
                       LT24_REFRESH_D      = (BASE_REG << LT24_REFRESH      ),
 
                       LT24_REFRESH_SYNC_D = (BASE_REG << LT24_REFRESH_SYNC ),
 
                       LT24_REFRESH_SYNC_D = (BASE_REG << LT24_REFRESH_SYNC ),
Line 259... Line 262... 
 
 
 
 
                       LUT_RAM_ADDR_D      = (BASE_REG << LUT_RAM_ADDR      ),
 
                       LUT_RAM_ADDR_D      = (BASE_REG << LUT_RAM_ADDR      ),
 
                       LUT_RAM_DATA_D      = (BASE_REG << LUT_RAM_DATA      ),
 
                       LUT_RAM_DATA_D      = (BASE_REG << LUT_RAM_DATA      ),
 
 
 
 
 
                       FRAME_SELECT_D      = (BASE_REG << FRAME_SELECT      ),
 
                       FRAME_SELECT_D      = (BASE_REG << FRAME_SELECT      ),
 
                       FRAME0_PTR_HI_D     = (BASE_REG << FRAME0_PTR_HI     ),
 
 
 
                       FRAME0_PTR_LO_D     = (BASE_REG << FRAME0_PTR_LO     ),
 
                       FRAME0_PTR_LO_D     = (BASE_REG << FRAME0_PTR_LO     ),
 
                       FRAME1_PTR_HI_D     = (BASE_REG << FRAME1_PTR_HI     ),
 
                       FRAME0_PTR_HI_D     = (BASE_REG << FRAME0_PTR_HI     ),
 
                       FRAME1_PTR_LO_D     = (BASE_REG << FRAME1_PTR_LO     ),
 
                       FRAME1_PTR_LO_D     = (BASE_REG << FRAME1_PTR_LO     ),
 
                       FRAME2_PTR_HI_D     = (BASE_REG << FRAME2_PTR_HI     ),
 
                       FRAME1_PTR_HI_D     = (BASE_REG << FRAME1_PTR_HI     ),
 
                       FRAME2_PTR_LO_D     = (BASE_REG << FRAME2_PTR_LO     ),
 
                       FRAME2_PTR_LO_D     = (BASE_REG << FRAME2_PTR_LO     ),
 
                       FRAME3_PTR_HI_D     = (BASE_REG << FRAME3_PTR_HI     ),
 
                       FRAME2_PTR_HI_D     = (BASE_REG << FRAME2_PTR_HI     ),
 
                       FRAME3_PTR_LO_D     = (BASE_REG << FRAME3_PTR_LO     ),
 
                       FRAME3_PTR_LO_D     = (BASE_REG << FRAME3_PTR_LO     ),
 
 
 
                       FRAME3_PTR_HI_D     = (BASE_REG << FRAME3_PTR_HI     ),
 
 
 
 
 
                       VID_RAM0_CFG_D      = (BASE_REG << VID_RAM0_CFG      ),
 
                       VID_RAM0_CFG_D      = (BASE_REG << VID_RAM0_CFG      ),
 
                       VID_RAM0_WIDTH_D    = (BASE_REG << VID_RAM0_WIDTH    ),
 
                       VID_RAM0_WIDTH_D    = (BASE_REG << VID_RAM0_WIDTH    ),
 
                       VID_RAM0_ADDR_HI_D  = (BASE_REG << VID_RAM0_ADDR_HI  ),
 
 
 
                       VID_RAM0_ADDR_LO_D  = (BASE_REG << VID_RAM0_ADDR_LO  ),
 
                       VID_RAM0_ADDR_LO_D  = (BASE_REG << VID_RAM0_ADDR_LO  ),
 
 
 
                       VID_RAM0_ADDR_HI_D  = (BASE_REG << VID_RAM0_ADDR_HI  ),
 
                       VID_RAM0_DATA_D     = (BASE_REG << VID_RAM0_DATA     ),
 
                       VID_RAM0_DATA_D     = (BASE_REG << VID_RAM0_DATA     ),
 
 
 
 
 
                       VID_RAM1_CFG_D      = (BASE_REG << VID_RAM1_CFG      ),
 
                       VID_RAM1_CFG_D      = (BASE_REG << VID_RAM1_CFG      ),
 
                       VID_RAM1_WIDTH_D    = (BASE_REG << VID_RAM1_WIDTH    ),
 
                       VID_RAM1_WIDTH_D    = (BASE_REG << VID_RAM1_WIDTH    ),
 
                       VID_RAM1_ADDR_HI_D  = (BASE_REG << VID_RAM1_ADDR_HI  ),
 
 
 
                       VID_RAM1_ADDR_LO_D  = (BASE_REG << VID_RAM1_ADDR_LO  ),
 
                       VID_RAM1_ADDR_LO_D  = (BASE_REG << VID_RAM1_ADDR_LO  ),
 
 
 
                       VID_RAM1_ADDR_HI_D  = (BASE_REG << VID_RAM1_ADDR_HI  ),
 
                       VID_RAM1_DATA_D     = (BASE_REG << VID_RAM1_DATA     ),
 
                       VID_RAM1_DATA_D     = (BASE_REG << VID_RAM1_DATA     ),
 
 
 
 
 
                       GPU_CMD_D           = (BASE_REG << GPU_CMD           ),
 
                       GPU_CMD_LO_D        = (BASE_REG << GPU_CMD_LO        ),
 
 
 
                       GPU_CMD_HI_D        = (BASE_REG << GPU_CMD_HI        ),
 
                       GPU_STAT_D          = (BASE_REG << GPU_STAT          );
 
                       GPU_STAT_D          = (BASE_REG << GPU_STAT          );
 
 
 
 
 
 
 
 
 
//============================================================================
 
//============================================================================
 
// 2)  REGISTER DECODER
 
// 2)  REGISTER DECODER
Line 301... Line 305... 
                                (GFX_STATUS_D        &  {DEC_SZ{(reg_addr == GFX_STATUS        )}})  |
 
                                (GFX_STATUS_D        &  {DEC_SZ{(reg_addr == GFX_STATUS        )}})  |
 
                                (GFX_IRQ_D           &  {DEC_SZ{(reg_addr == GFX_IRQ           )}})  |
 
                                (GFX_IRQ_D           &  {DEC_SZ{(reg_addr == GFX_IRQ           )}})  |
 
 
 
 
 
                                (DISPLAY_WIDTH_D     &  {DEC_SZ{(reg_addr == DISPLAY_WIDTH     )}})  |
 
                                (DISPLAY_WIDTH_D     &  {DEC_SZ{(reg_addr == DISPLAY_WIDTH     )}})  |
 
                                (DISPLAY_HEIGHT_D    &  {DEC_SZ{(reg_addr == DISPLAY_HEIGHT    )}})  |
 
                                (DISPLAY_HEIGHT_D    &  {DEC_SZ{(reg_addr == DISPLAY_HEIGHT    )}})  |
 
                                (DISPLAY_SIZE_HI_D   &  {DEC_SZ{(reg_addr == DISPLAY_SIZE_HI   )}})  |
 
 
 
                                (DISPLAY_SIZE_LO_D   &  {DEC_SZ{(reg_addr == DISPLAY_SIZE_LO   )}})  |
 
                                (DISPLAY_SIZE_LO_D   &  {DEC_SZ{(reg_addr == DISPLAY_SIZE_LO   )}})  |
 
 
 
                                (DISPLAY_SIZE_HI_D   &  {DEC_SZ{(reg_addr == DISPLAY_SIZE_HI   )}})  |
 
                                (DISPLAY_CFG_D       &  {DEC_SZ{(reg_addr == DISPLAY_CFG       )}})  |
 
                                (DISPLAY_CFG_D       &  {DEC_SZ{(reg_addr == DISPLAY_CFG       )}})  |
 
 
 
 
 
                                (LT24_CFG_D          &  {DEC_SZ{(reg_addr == LT24_CFG          )}})  |
 
                                (LT24_CFG_D          &  {DEC_SZ{(reg_addr == LT24_CFG          )}})  |
 
                                (LT24_REFRESH_D      &  {DEC_SZ{(reg_addr == LT24_REFRESH      )}})  |
 
                                (LT24_REFRESH_D      &  {DEC_SZ{(reg_addr == LT24_REFRESH      )}})  |
 
                                (LT24_REFRESH_SYNC_D &  {DEC_SZ{(reg_addr == LT24_REFRESH_SYNC )}})  |
 
                                (LT24_REFRESH_SYNC_D &  {DEC_SZ{(reg_addr == LT24_REFRESH_SYNC )}})  |
Line 317... Line 321... 
 
 
 
 
                                (LUT_RAM_ADDR_D      &  {DEC_SZ{(reg_addr == LUT_RAM_ADDR      )}})  |
 
                                (LUT_RAM_ADDR_D      &  {DEC_SZ{(reg_addr == LUT_RAM_ADDR      )}})  |
 
                                (LUT_RAM_DATA_D      &  {DEC_SZ{(reg_addr == LUT_RAM_DATA      )}})  |
 
                                (LUT_RAM_DATA_D      &  {DEC_SZ{(reg_addr == LUT_RAM_DATA      )}})  |
 
 
 
 
 
                                (FRAME_SELECT_D      &  {DEC_SZ{(reg_addr == FRAME_SELECT      )}})  |
 
                                (FRAME_SELECT_D      &  {DEC_SZ{(reg_addr == FRAME_SELECT      )}})  |
 
                                (FRAME0_PTR_HI_D     &  {DEC_SZ{(reg_addr == FRAME0_PTR_HI     )}})  |
 
 
 
                                (FRAME0_PTR_LO_D     &  {DEC_SZ{(reg_addr == FRAME0_PTR_LO     )}})  |
 
                                (FRAME0_PTR_LO_D     &  {DEC_SZ{(reg_addr == FRAME0_PTR_LO     )}})  |
 
                                (FRAME1_PTR_HI_D     &  {DEC_SZ{(reg_addr == FRAME1_PTR_HI     )}})  |
 
                                (FRAME0_PTR_HI_D     &  {DEC_SZ{(reg_addr == FRAME0_PTR_HI     )}})  |
 
                                (FRAME1_PTR_LO_D     &  {DEC_SZ{(reg_addr == FRAME1_PTR_LO     )}})  |
 
                                (FRAME1_PTR_LO_D     &  {DEC_SZ{(reg_addr == FRAME1_PTR_LO     )}})  |
 
                                (FRAME2_PTR_HI_D     &  {DEC_SZ{(reg_addr == FRAME2_PTR_HI     )}})  |
 
                                (FRAME1_PTR_HI_D     &  {DEC_SZ{(reg_addr == FRAME1_PTR_HI     )}})  |
 
                                (FRAME2_PTR_LO_D     &  {DEC_SZ{(reg_addr == FRAME2_PTR_LO     )}})  |
 
                                (FRAME2_PTR_LO_D     &  {DEC_SZ{(reg_addr == FRAME2_PTR_LO     )}})  |
 
                                (FRAME3_PTR_HI_D     &  {DEC_SZ{(reg_addr == FRAME3_PTR_HI     )}})  |
 
                                (FRAME2_PTR_HI_D     &  {DEC_SZ{(reg_addr == FRAME2_PTR_HI     )}})  |
 
                                (FRAME3_PTR_LO_D     &  {DEC_SZ{(reg_addr == FRAME3_PTR_LO     )}})  |
 
                                (FRAME3_PTR_LO_D     &  {DEC_SZ{(reg_addr == FRAME3_PTR_LO     )}})  |
 
 
 
                                (FRAME3_PTR_HI_D     &  {DEC_SZ{(reg_addr == FRAME3_PTR_HI     )}})  |
 
 
 
 
 
                                (VID_RAM0_CFG_D      &  {DEC_SZ{(reg_addr == VID_RAM0_CFG      )}})  |
 
                                (VID_RAM0_CFG_D      &  {DEC_SZ{(reg_addr == VID_RAM0_CFG      )}})  |
 
                                (VID_RAM0_WIDTH_D    &  {DEC_SZ{(reg_addr == VID_RAM0_WIDTH    )}})  |
 
                                (VID_RAM0_WIDTH_D    &  {DEC_SZ{(reg_addr == VID_RAM0_WIDTH    )}})  |
 
                                (VID_RAM0_ADDR_HI_D  &  {DEC_SZ{(reg_addr == VID_RAM0_ADDR_HI  )}})  |
 
 
 
                                (VID_RAM0_ADDR_LO_D  &  {DEC_SZ{(reg_addr == VID_RAM0_ADDR_LO  )}})  |
 
                                (VID_RAM0_ADDR_LO_D  &  {DEC_SZ{(reg_addr == VID_RAM0_ADDR_LO  )}})  |
 
 
 
                                (VID_RAM0_ADDR_HI_D  &  {DEC_SZ{(reg_addr == VID_RAM0_ADDR_HI  )}})  |
 
                                (VID_RAM0_DATA_D     &  {DEC_SZ{(reg_addr == VID_RAM0_DATA     )}})  |
 
                                (VID_RAM0_DATA_D     &  {DEC_SZ{(reg_addr == VID_RAM0_DATA     )}})  |
 
 
 
 
 
                                (VID_RAM1_CFG_D      &  {DEC_SZ{(reg_addr == VID_RAM1_CFG      )}})  |
 
                                (VID_RAM1_CFG_D      &  {DEC_SZ{(reg_addr == VID_RAM1_CFG      )}})  |
 
                                (VID_RAM1_WIDTH_D    &  {DEC_SZ{(reg_addr == VID_RAM1_WIDTH    )}})  |
 
                                (VID_RAM1_WIDTH_D    &  {DEC_SZ{(reg_addr == VID_RAM1_WIDTH    )}})  |
 
                                (VID_RAM1_ADDR_HI_D  &  {DEC_SZ{(reg_addr == VID_RAM1_ADDR_HI  )}})  |
 
 
 
                                (VID_RAM1_ADDR_LO_D  &  {DEC_SZ{(reg_addr == VID_RAM1_ADDR_LO  )}})  |
 
                                (VID_RAM1_ADDR_LO_D  &  {DEC_SZ{(reg_addr == VID_RAM1_ADDR_LO  )}})  |
 
 
 
                                (VID_RAM1_ADDR_HI_D  &  {DEC_SZ{(reg_addr == VID_RAM1_ADDR_HI  )}})  |
 
                                (VID_RAM1_DATA_D     &  {DEC_SZ{(reg_addr == VID_RAM1_DATA     )}})  |
 
                                (VID_RAM1_DATA_D     &  {DEC_SZ{(reg_addr == VID_RAM1_DATA     )}})  |
 
 
 
 
 
                                (GPU_CMD_D           &  {DEC_SZ{(reg_addr == GPU_CMD           )}})  |
 
                                (GPU_CMD_LO_D        &  {DEC_SZ{(reg_addr == GPU_CMD_LO        )}})  |
 
 
 
                                (GPU_CMD_HI_D        &  {DEC_SZ{(reg_addr == GPU_CMD_HI        )}})  |
 
                                (GPU_STAT_D          &  {DEC_SZ{(reg_addr == GPU_STAT          )}});
 
                                (GPU_STAT_D          &  {DEC_SZ{(reg_addr == GPU_STAT          )}});
 
 
 
 
 
// Read/Write probes
 
// Read/Write probes
 
wire               reg_write =  |per_we_i & reg_sel;
 
wire               reg_write =  |per_we_i & reg_sel;
 
wire               reg_read  = ~|per_we_i & reg_sel;
 
wire               reg_read  = ~|per_we_i & reg_sel;
Line 365... Line 370... 
wire [`APIX_MSB:0] vid_ram0_base_addr;
 
wire [`APIX_MSB:0] vid_ram0_base_addr;
 
wire [`APIX_MSB:0] vid_ram1_base_addr;
 
wire [`APIX_MSB:0] vid_ram1_base_addr;
 
`ifdef WITH_EXTRA_LUT_BANK
 
`ifdef WITH_EXTRA_LUT_BANK
 
reg                lut_bank_select;
 
reg                lut_bank_select;
 
`endif
 
`endif
 
reg                vid_ram0_addr_lo_wr_dly;
 
 
 
reg                vid_ram1_addr_lo_wr_dly;
 
 
 
wire               gpu_fifo_done_evt;
 
wire               gpu_fifo_done_evt;
 
wire               gpu_fifo_ovfl_evt;
 
wire               gpu_fifo_ovfl_evt;
 
 
 
 
 
 
 
 
 
//============================================================================
 
//============================================================================
Line 1086... Line 1089... 
    .mclk                    ( mclk                     ),   // Main system clock
 
    .mclk                    ( mclk                     ),   // Main system clock
 
    .puc_rst                 ( puc_rst                  ),   // Main system reset
 
    .puc_rst                 ( puc_rst                  ),   // Main system reset
 
 
 
 
 
    .vid_ram_cfg_wr_i        ( reg_wr[VID_RAM0_CFG]     ),   // VID_RAM0_CFG     Write strobe
 
    .vid_ram_cfg_wr_i        ( reg_wr[VID_RAM0_CFG]     ),   // VID_RAM0_CFG     Write strobe
 
    .vid_ram_width_wr_i      ( reg_wr[VID_RAM0_WIDTH]   ),   // VID_RAM0_WIDTH   Write strobe
 
    .vid_ram_width_wr_i      ( reg_wr[VID_RAM0_WIDTH]   ),   // VID_RAM0_WIDTH   Write strobe
 
`ifdef VRAM_BIGGER_4_KW
 
 
 
    .vid_ram_addr_hi_wr_i    ( reg_wr[VID_RAM0_ADDR_HI] ),   // VID_RAM0_ADDR_HI Write strobe
 
    .vid_ram_addr_hi_wr_i    ( reg_wr[VID_RAM0_ADDR_HI] ),   // VID_RAM0_ADDR_HI Write strobe
 
`endif
 
 
 
    .vid_ram_addr_lo_wr_i    ( reg_wr[VID_RAM0_ADDR_LO] ),   // VID_RAM0_ADDR_LO Write strobe
 
    .vid_ram_addr_lo_wr_i    ( reg_wr[VID_RAM0_ADDR_LO] ),   // VID_RAM0_ADDR_LO Write strobe
 
    .vid_ram_data_wr_i       ( reg_wr[VID_RAM0_DATA]    ),   // VID_RAM0_DATA    Write strobe
 
    .vid_ram_data_wr_i       ( reg_wr[VID_RAM0_DATA]    ),   // VID_RAM0_DATA    Write strobe
 
    .vid_ram_data_rd_i       ( reg_rd[VID_RAM0_DATA]    ),   // VID_RAM0_DATA    Read  strobe
 
    .vid_ram_data_rd_i       ( reg_rd[VID_RAM0_DATA]    ),   // VID_RAM0_DATA    Read  strobe
 
 
 
 
 
    .dbg_freeze_i            ( dbg_freeze_i             ),   // Freeze auto-increment on read when CPU stopped
 
    .dbg_freeze_i            ( dbg_freeze_i             ),   // Freeze auto-increment on read when CPU stopped
Line 1146... Line 1147... 
    .mclk                    ( mclk                     ),   // Main system clock
 
    .mclk                    ( mclk                     ),   // Main system clock
 
    .puc_rst                 ( puc_rst                  ),   // Main system reset
 
    .puc_rst                 ( puc_rst                  ),   // Main system reset
 
 
 
 
 
    .vid_ram_cfg_wr_i        ( reg_wr[VID_RAM1_CFG]     ),   // VID_RAM1_CFG     Write strobe
 
    .vid_ram_cfg_wr_i        ( reg_wr[VID_RAM1_CFG]     ),   // VID_RAM1_CFG     Write strobe
 
    .vid_ram_width_wr_i      ( reg_wr[VID_RAM1_WIDTH]   ),   // VID_RAM1_WIDTH   Write strobe
 
    .vid_ram_width_wr_i      ( reg_wr[VID_RAM1_WIDTH]   ),   // VID_RAM1_WIDTH   Write strobe
 
`ifdef VRAM_BIGGER_4_KW
 
 
 
    .vid_ram_addr_hi_wr_i    ( reg_wr[VID_RAM1_ADDR_HI] ),   // VID_RAM1_ADDR_HI Write strobe
 
    .vid_ram_addr_hi_wr_i    ( reg_wr[VID_RAM1_ADDR_HI] ),   // VID_RAM1_ADDR_HI Write strobe
 
`endif
 
 
 
    .vid_ram_addr_lo_wr_i    ( reg_wr[VID_RAM1_ADDR_LO] ),   // VID_RAM1_ADDR_LO Write strobe
 
    .vid_ram_addr_lo_wr_i    ( reg_wr[VID_RAM1_ADDR_LO] ),   // VID_RAM1_ADDR_LO Write strobe
 
    .vid_ram_data_wr_i       ( reg_wr[VID_RAM1_DATA]    ),   // VID_RAM1_DATA    Write strobe
 
    .vid_ram_data_wr_i       ( reg_wr[VID_RAM1_DATA]    ),   // VID_RAM1_DATA    Write strobe
 
    .vid_ram_data_rd_i       ( reg_rd[VID_RAM1_DATA]    ),   // VID_RAM1_DATA    Read  strobe
 
    .vid_ram_data_rd_i       ( reg_rd[VID_RAM1_DATA]    ),   // VID_RAM1_DATA    Read  strobe
 
 
 
 
 
    .dbg_freeze_i            ( dbg_freeze_i             ),   // Freeze auto-increment on read when CPU stopped
 
    .dbg_freeze_i            ( dbg_freeze_i             ),   // Freeze auto-increment on read when CPU stopped
Line 1171... Line 1170... 
//------------------------------------------------
 
//------------------------------------------------
 
// GPU Interface (GPU_CMD/GPU_STAT) Registers
 
// GPU Interface (GPU_CMD/GPU_STAT) Registers
 
//------------------------------------------------
 
//------------------------------------------------
 
 
 
 
 
wire [3:0] gpu_stat_fifo_cnt;
 
wire [3:0] gpu_stat_fifo_cnt;
 
 
 
wire [3:0] gpu_stat_fifo_cnt_empty;
 
wire       gpu_stat_fifo_empty;
 
wire       gpu_stat_fifo_empty;
 
wire       gpu_stat_fifo_full;
 
wire       gpu_stat_fifo_full;
 
 
 
wire       gpu_stat_fifo_full_less_2;
 
 
 
wire       gpu_stat_fifo_full_less_3;
 
 
 
 
 
ogfx_reg_fifo ogfx_reg_fifo_gpu_inst (
 
ogfx_reg_fifo ogfx_reg_fifo_gpu_inst (
 
 
 
 
 
// OUTPUTs
 
// OUTPUTs
 
    .fifo_cnt_o              ( gpu_stat_fifo_cnt        ),   // Fifo counter
 
    .fifo_cnt_o              ( gpu_stat_fifo_cnt        ),   // Fifo counter
 
    .fifo_data_o             ( gpu_data_o               ),   // Read data output
 
    .fifo_data_o             ( gpu_data_o               ),   // Read data output
 
    .fifo_done_evt_o         ( gpu_fifo_done_evt        ),   // Fifo has been emptied
 
    .fifo_done_evt_o         ( gpu_fifo_done_evt        ),   // Fifo has been emptied
 
    .fifo_empty_o            ( gpu_stat_fifo_empty      ),   // Fifo is currentely empty
 
    .fifo_empty_o            ( gpu_stat_fifo_empty      ),   // Fifo is currentely empty
 
 
 
    .fifo_empty_cnt_o        ( gpu_stat_fifo_cnt_empty  ),   // Fifo empty words counter
 
    .fifo_full_o             ( gpu_stat_fifo_full       ),   // Fifo is currentely full
 
    .fifo_full_o             ( gpu_stat_fifo_full       ),   // Fifo is currentely full
 
    .fifo_ovfl_evt_o         ( gpu_fifo_ovfl_evt        ),   // Fifo overflow event
 
    .fifo_ovfl_evt_o         ( gpu_fifo_ovfl_evt        ),   // Fifo overflow event
 
 
 
 
 
// INPUTs
 
// INPUTs
 
    .mclk                    ( mclk                     ),   // Main system clock
 
    .mclk                    ( mclk                     ),   // Main system clock
 
    .puc_rst                 ( puc_rst                  ),   // Main system reset
 
    .puc_rst                 ( puc_rst                  ),   // Main system reset
 
 
 
 
 
    .fifo_data_i             ( per_din_i                ),   // Read data input
 
    .fifo_data_i             ( per_din_i                ),   // Read data input
 
    .fifo_enable_i           ( gpu_enable_o             ),   // Enable fifo (flushed when disabled)
 
    .fifo_enable_i           ( gpu_enable_o             ),   // Enable fifo (flushed when disabled)
 
    .fifo_pop_i              ( gpu_get_data_i           ),   // Pop data from the fifo
 
    .fifo_pop_i              ( gpu_get_data_i           ),   // Pop data from the fifo
 
    .fifo_push_i             ( reg_wr[GPU_CMD]          )    // Push new data to the fifo
 
    .fifo_push_i             ( reg_wr[GPU_CMD_LO] |
 
 
 
                               reg_wr[GPU_CMD_HI]       )    // Push new data to the fifo
 
);
 
);
 
 
 
 
 
assign      gpu_data_avail_o = ~gpu_stat_fifo_empty;
 
assign      gpu_data_avail_o = ~gpu_stat_fifo_empty;
 
 
 
 
 
wire [15:0] gpu_stat         = {10'h000, gpu_stat_fifo_full, gpu_stat_fifo_empty, gpu_stat_fifo_cnt};
 
wire        gpu_busy         = ~gpu_stat_fifo_empty | gpu_dma_busy_i;
 
 
 
 
 
 
 
wire [15:0] gpu_stat         = {gpu_busy, 2'b00, gpu_dma_busy_i,
 
 
 
                                2'b00   , gpu_stat_fifo_full, gpu_stat_fifo_empty,
 
 
 
                                gpu_stat_fifo_cnt, gpu_stat_fifo_cnt_empty};
 
 
 
 
 
 
 
 
 
//============================================================================
 
//============================================================================
 
// 4) DATA OUTPUT GENERATION
 
// 4) DATA OUTPUT GENERATION
 
//============================================================================
 
//============================================================================
Line 1210... Line 1218... 
wire [15:0] gfx_status_read        = gfx_status           & {16{reg_rd[GFX_STATUS        ]}};
 
wire [15:0] gfx_status_read        = gfx_status           & {16{reg_rd[GFX_STATUS        ]}};
 
wire [15:0] gfx_irq_read           = gfx_irq              & {16{reg_rd[GFX_IRQ           ]}};
 
wire [15:0] gfx_irq_read           = gfx_irq              & {16{reg_rd[GFX_IRQ           ]}};
 
 
 
 
 
wire [15:0] display_width_read     = display_width_rd     & {16{reg_rd[DISPLAY_WIDTH     ]}};
 
wire [15:0] display_width_read     = display_width_rd     & {16{reg_rd[DISPLAY_WIDTH     ]}};
 
wire [15:0] display_height_read    = display_height_rd    & {16{reg_rd[DISPLAY_HEIGHT    ]}};
 
wire [15:0] display_height_read    = display_height_rd    & {16{reg_rd[DISPLAY_HEIGHT    ]}};
 
 
 
wire [15:0] display_size_lo_read   = display_size_lo_rd   & {16{reg_rd[DISPLAY_SIZE_LO   ]}};
 
`ifdef WITH_DISPLAY_SIZE_HI
 
`ifdef WITH_DISPLAY_SIZE_HI
 
wire [15:0] display_size_hi_read   = display_size_hi_rd   & {16{reg_rd[DISPLAY_SIZE_HI   ]}};
 
wire [15:0] display_size_hi_read   = display_size_hi_rd   & {16{reg_rd[DISPLAY_SIZE_HI   ]}};
 
`endif
 
`endif
 
wire [15:0] display_size_lo_read   = display_size_lo_rd   & {16{reg_rd[DISPLAY_SIZE_LO   ]}};
 
 
 
wire [15:0] display_cfg_read       = display_cfg          & {16{reg_rd[DISPLAY_CFG       ]}};
 
wire [15:0] display_cfg_read       = display_cfg          & {16{reg_rd[DISPLAY_CFG       ]}};
 
 
 
 
 
wire [15:0] lt24_cfg_read          = lt24_cfg             & {16{reg_rd[LT24_CFG          ]}};
 
wire [15:0] lt24_cfg_read          = lt24_cfg             & {16{reg_rd[LT24_CFG          ]}};
 
wire [15:0] lt24_refresh_read      = lt24_refresh         & {16{reg_rd[LT24_REFRESH      ]}};
 
wire [15:0] lt24_refresh_read      = lt24_refresh         & {16{reg_rd[LT24_REFRESH      ]}};
 
wire [15:0] lt24_refresh_sync_read = lt24_refresh_sync    & {16{reg_rd[LT24_REFRESH_SYNC ]}};
 
wire [15:0] lt24_refresh_sync_read = lt24_refresh_sync    & {16{reg_rd[LT24_REFRESH_SYNC ]}};
Line 1228... Line 1236... 
 
 
 
 
wire [15:0] lut_ram_addr_read      = lut_ram_addr_rd      & {16{reg_rd[LUT_RAM_ADDR      ]}};
 
wire [15:0] lut_ram_addr_read      = lut_ram_addr_rd      & {16{reg_rd[LUT_RAM_ADDR      ]}};
 
wire [15:0] lut_ram_data_read      = lut_ram_data         & {16{reg_rd[LUT_RAM_DATA      ]}};
 
wire [15:0] lut_ram_data_read      = lut_ram_data         & {16{reg_rd[LUT_RAM_DATA      ]}};
 
 
 
 
 
wire [15:0] frame_select_read      = frame_select         & {16{reg_rd[FRAME_SELECT      ]}};
 
wire [15:0] frame_select_read      = frame_select         & {16{reg_rd[FRAME_SELECT      ]}};
 
 
 
wire [15:0] frame0_ptr_lo_read     = frame0_ptr_lo_rd     & {16{reg_rd[FRAME0_PTR_LO     ]}};
 
`ifdef VRAM_BIGGER_4_KW
 
`ifdef VRAM_BIGGER_4_KW
 
wire [15:0] frame0_ptr_hi_read     = frame0_ptr_hi_rd     & {16{reg_rd[FRAME0_PTR_HI     ]}};
 
wire [15:0] frame0_ptr_hi_read     = frame0_ptr_hi_rd     & {16{reg_rd[FRAME0_PTR_HI     ]}};
 
`endif
 
`endif
 
wire [15:0] frame0_ptr_lo_read     = frame0_ptr_lo_rd     & {16{reg_rd[FRAME0_PTR_LO     ]}};
 
 
 
`ifdef WITH_FRAME1_POINTER
 
`ifdef WITH_FRAME1_POINTER
 
 
 
  wire [15:0] frame1_ptr_lo_read   = frame1_ptr_lo_rd     & {16{reg_rd[FRAME1_PTR_LO     ]}};
 
  `ifdef VRAM_BIGGER_4_KW
 
  `ifdef VRAM_BIGGER_4_KW
 
  wire [15:0] frame1_ptr_hi_read   = frame1_ptr_hi_rd     & {16{reg_rd[FRAME1_PTR_HI     ]}};
 
  wire [15:0] frame1_ptr_hi_read   = frame1_ptr_hi_rd     & {16{reg_rd[FRAME1_PTR_HI     ]}};
 
  `endif
 
  `endif
 
  wire [15:0] frame1_ptr_lo_read   = frame1_ptr_lo_rd     & {16{reg_rd[FRAME1_PTR_LO     ]}};
 
 
 
`endif
 
`endif
 
`ifdef WITH_FRAME2_POINTER
 
`ifdef WITH_FRAME2_POINTER
 
 
 
  wire [15:0] frame2_ptr_lo_read   = frame2_ptr_lo_rd     & {16{reg_rd[FRAME2_PTR_LO     ]}};
 
  `ifdef VRAM_BIGGER_4_KW
 
  `ifdef VRAM_BIGGER_4_KW
 
  wire [15:0] frame2_ptr_hi_read   = frame2_ptr_hi_rd     & {16{reg_rd[FRAME2_PTR_HI     ]}};
 
  wire [15:0] frame2_ptr_hi_read   = frame2_ptr_hi_rd     & {16{reg_rd[FRAME2_PTR_HI     ]}};
 
  `endif
 
  `endif
 
  wire [15:0] frame2_ptr_lo_read   = frame2_ptr_lo_rd     & {16{reg_rd[FRAME2_PTR_LO     ]}};
 
 
 
`endif
 
`endif
 
`ifdef WITH_FRAME3_POINTER
 
`ifdef WITH_FRAME3_POINTER
 
 
 
  wire [15:0] frame3_ptr_lo_read   = frame3_ptr_lo_rd     & {16{reg_rd[FRAME3_PTR_LO     ]}};
 
  `ifdef VRAM_BIGGER_4_KW
 
  `ifdef VRAM_BIGGER_4_KW
 
  wire [15:0] frame3_ptr_hi_read   = frame3_ptr_hi_rd     & {16{reg_rd[FRAME3_PTR_HI     ]}};
 
  wire [15:0] frame3_ptr_hi_read   = frame3_ptr_hi_rd     & {16{reg_rd[FRAME3_PTR_HI     ]}};
 
  `endif
 
  `endif
 
  wire [15:0] frame3_ptr_lo_read   = frame3_ptr_lo_rd     & {16{reg_rd[FRAME3_PTR_LO     ]}};
 
 
 
`endif
 
`endif
 
wire [15:0] vid_ram0_cfg_read      = vid_ram0_cfg         & {16{reg_rd[VID_RAM0_CFG      ]}};
 
wire [15:0] vid_ram0_cfg_read      = vid_ram0_cfg         & {16{reg_rd[VID_RAM0_CFG      ]}};
 
wire [15:0] vid_ram0_width_read    = vid_ram0_width       & {16{reg_rd[VID_RAM0_WIDTH    ]}};
 
wire [15:0] vid_ram0_width_read    = vid_ram0_width       & {16{reg_rd[VID_RAM0_WIDTH    ]}};
 
 
 
wire [15:0] vid_ram0_addr_lo_read  = vid_ram0_addr_lo     & {16{reg_rd[VID_RAM0_ADDR_LO  ]}};
 
`ifdef VRAM_BIGGER_4_KW
 
`ifdef VRAM_BIGGER_4_KW
 
wire [15:0] vid_ram0_addr_hi_read  = vid_ram0_addr_hi     & {16{reg_rd[VID_RAM0_ADDR_HI  ]}};
 
wire [15:0] vid_ram0_addr_hi_read  = vid_ram0_addr_hi     & {16{reg_rd[VID_RAM0_ADDR_HI  ]}};
 
`endif
 
`endif
 
wire [15:0] vid_ram0_addr_lo_read  = vid_ram0_addr_lo     & {16{reg_rd[VID_RAM0_ADDR_LO  ]}};
 
 
 
wire [15:0] vid_ram0_data_read     = vid_ram0_data        & {16{reg_rd[VID_RAM0_DATA     ]}};
 
wire [15:0] vid_ram0_data_read     = vid_ram0_data        & {16{reg_rd[VID_RAM0_DATA     ]}};
 
 
 
 
 
wire [15:0] vid_ram1_cfg_read      = vid_ram1_cfg         & {16{reg_rd[VID_RAM1_CFG      ]}};
 
wire [15:0] vid_ram1_cfg_read      = vid_ram1_cfg         & {16{reg_rd[VID_RAM1_CFG      ]}};
 
wire [15:0] vid_ram1_width_read    = vid_ram1_width       & {16{reg_rd[VID_RAM1_WIDTH    ]}};
 
wire [15:0] vid_ram1_width_read    = vid_ram1_width       & {16{reg_rd[VID_RAM1_WIDTH    ]}};
 
 
 
wire [15:0] vid_ram1_addr_lo_read  = vid_ram1_addr_lo     & {16{reg_rd[VID_RAM1_ADDR_LO  ]}};
 
`ifdef VRAM_BIGGER_4_KW
 
`ifdef VRAM_BIGGER_4_KW
 
wire [15:0] vid_ram1_addr_hi_read  = vid_ram1_addr_hi     & {16{reg_rd[VID_RAM1_ADDR_HI  ]}};
 
wire [15:0] vid_ram1_addr_hi_read  = vid_ram1_addr_hi     & {16{reg_rd[VID_RAM1_ADDR_HI  ]}};
 
`endif
 
`endif
 
wire [15:0] vid_ram1_addr_lo_read  = vid_ram1_addr_lo     & {16{reg_rd[VID_RAM1_ADDR_LO  ]}};
 
 
 
wire [15:0] vid_ram1_data_read     = vid_ram1_data        & {16{reg_rd[VID_RAM1_DATA     ]}};
 
wire [15:0] vid_ram1_data_read     = vid_ram1_data        & {16{reg_rd[VID_RAM1_DATA     ]}};
 
wire [15:0] gpu_cmd_read           = 16'h0000             & {16{reg_rd[GPU_CMD           ]}};
 
wire [15:0] gpu_cmd_lo_read        = 16'h0000             & {16{reg_rd[GPU_CMD_LO        ]}};
 
 
 
wire [15:0] gpu_cmd_hi_read        = 16'h0000             & {16{reg_rd[GPU_CMD_HI        ]}};
 
wire [15:0] gpu_stat_read          = gpu_stat             & {16{reg_rd[GPU_STAT          ]}};
 
wire [15:0] gpu_stat_read          = gpu_stat             & {16{reg_rd[GPU_STAT          ]}};
 
 
 
 
 
 
 
 
 
wire [15:0] per_dout_o             = gfx_ctrl_read          |
 
wire [15:0] per_dout_o             = gfx_ctrl_read          |
 
                                     gfx_status_read        |
 
                                     gfx_status_read        |
 
                                     gfx_irq_read           |
 
                                     gfx_irq_read           |
 
 
 
 
 
                                     display_width_read     |
 
                                     display_width_read     |
 
                                     display_height_read    |
 
                                     display_height_read    |
 
 
 
                                     display_size_lo_read   |
 
                                  `ifdef WITH_DISPLAY_SIZE_HI
 
                                  `ifdef WITH_DISPLAY_SIZE_HI
 
                                     display_size_hi_read   |
 
                                     display_size_hi_read   |
 
                                  `endif
 
                                  `endif
 
                                     display_size_lo_read   |
 
 
 
                                     display_cfg_read       |
 
                                     display_cfg_read       |
 
 
 
 
 
                                     lt24_cfg_read          |
 
                                     lt24_cfg_read          |
 
                                     lt24_refresh_read      |
 
                                     lt24_refresh_read      |
 
                                     lt24_refresh_sync_read |
 
                                     lt24_refresh_sync_read |
Line 1293... Line 1302... 
 
 
 
 
                                     lut_ram_addr_read      |
 
                                     lut_ram_addr_read      |
 
                                     lut_ram_data_read      |
 
                                     lut_ram_data_read      |
 
 
 
 
 
                                     frame_select_read      |
 
                                     frame_select_read      |
 
 
 
                                     frame0_ptr_lo_read     |
 
                                  `ifdef VRAM_BIGGER_4_KW
 
                                  `ifdef VRAM_BIGGER_4_KW
 
                                     frame0_ptr_hi_read     |
 
                                     frame0_ptr_hi_read     |
 
                                  `endif
 
                                  `endif
 
                                     frame0_ptr_lo_read     |
 
 
 
                                `ifdef WITH_FRAME1_POINTER
 
                                `ifdef WITH_FRAME1_POINTER
 
 
 
                                     frame1_ptr_lo_read     |
 
                                  `ifdef VRAM_BIGGER_4_KW
 
                                  `ifdef VRAM_BIGGER_4_KW
 
                                     frame1_ptr_hi_read     |
 
                                     frame1_ptr_hi_read     |
 
                                  `endif
 
                                  `endif
 
                                     frame1_ptr_lo_read     |
 
 
 
                                `endif
 
                                `endif
 
                                `ifdef WITH_FRAME2_POINTER
 
                                `ifdef WITH_FRAME2_POINTER
 
 
 
                                     frame2_ptr_lo_read     |
 
                                  `ifdef VRAM_BIGGER_4_KW
 
                                  `ifdef VRAM_BIGGER_4_KW
 
                                     frame2_ptr_hi_read     |
 
                                     frame2_ptr_hi_read     |
 
                                  `endif
 
                                  `endif
 
                                     frame2_ptr_lo_read     |
 
 
 
                                `endif
 
                                `endif
 
                                `ifdef WITH_FRAME3_POINTER
 
                                `ifdef WITH_FRAME3_POINTER
 
 
 
                                     frame3_ptr_lo_read     |
 
                                  `ifdef VRAM_BIGGER_4_KW
 
                                  `ifdef VRAM_BIGGER_4_KW
 
                                     frame3_ptr_hi_read     |
 
                                     frame3_ptr_hi_read     |
 
                                  `endif
 
                                  `endif
 
                                     frame3_ptr_lo_read     |
 
 
 
                                `endif
 
                                `endif
 
                                     vid_ram0_cfg_read      |
 
                                     vid_ram0_cfg_read      |
 
                                     vid_ram0_width_read    |
 
                                     vid_ram0_width_read    |
 
 
 
                                     vid_ram0_addr_lo_read  |
 
                                  `ifdef VRAM_BIGGER_4_KW
 
                                  `ifdef VRAM_BIGGER_4_KW
 
                                     vid_ram0_addr_hi_read  |
 
                                     vid_ram0_addr_hi_read  |
 
                                  `endif
 
                                  `endif
 
                                     vid_ram0_addr_lo_read  |
 
 
 
                                     vid_ram0_data_read     |
 
                                     vid_ram0_data_read     |
 
 
 
 
 
                                     vid_ram1_cfg_read      |
 
                                     vid_ram1_cfg_read      |
 
                                     vid_ram1_width_read    |
 
                                     vid_ram1_width_read    |
 
 
 
                                     vid_ram1_addr_lo_read  |
 
                                  `ifdef VRAM_BIGGER_4_KW
 
                                  `ifdef VRAM_BIGGER_4_KW
 
                                     vid_ram1_addr_hi_read  |
 
                                     vid_ram1_addr_hi_read  |
 
                                  `endif
 
                                  `endif
 
                                     vid_ram1_addr_lo_read  |
 
 
 
                                     vid_ram1_data_read     |
 
                                     vid_ram1_data_read     |
 
                                     gpu_cmd_read           |
 
                                     gpu_cmd_lo_read        |
 
 
 
                                     gpu_cmd_hi_read        |
 
                                     gpu_stat_read;
 
                                     gpu_stat_read;
 
 
 
 
 
 
 
 
 
//============================================================================
 
//============================================================================
 
// 5) VIDEO MEMORY INTERFACE
 
// 5) VIDEO MEMORY INTERFACE

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