| Line 61... |
Line 61... |
mclk, // Main system clock
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mclk, // Main system clock
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puc_rst, // Main system reset
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puc_rst, // Main system reset
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vid_ram_cfg_wr_i, // VID_RAMx_CFG Write strobe
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vid_ram_cfg_wr_i, // VID_RAMx_CFG Write strobe
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vid_ram_width_wr_i, // VID_RAMx_WIDTH Write strobe
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vid_ram_width_wr_i, // VID_RAMx_WIDTH Write strobe
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`ifdef VRAM_BIGGER_4_KW
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vid_ram_addr_hi_wr_i, // VID_RAMx_ADDR_HI Write strobe
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vid_ram_addr_hi_wr_i, // VID_RAMx_ADDR_HI Write strobe
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`endif
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vid_ram_addr_lo_wr_i, // VID_RAMx_ADDR_LO Write strobe
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vid_ram_addr_lo_wr_i, // VID_RAMx_ADDR_LO Write strobe
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vid_ram_data_wr_i, // VID_RAMx_DATA Write strobe
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vid_ram_data_wr_i, // VID_RAMx_DATA Write strobe
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vid_ram_data_rd_i, // VID_RAMx_DATA Read strobe
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vid_ram_data_rd_i, // VID_RAMx_DATA Read strobe
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dbg_freeze_i, // Freeze auto-increment on read when CPU stopped
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dbg_freeze_i, // Freeze auto-increment on read when CPU stopped
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| Line 104... |
Line 102... |
input mclk; // Main system clock
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input mclk; // Main system clock
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input puc_rst; // Main system reset
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input puc_rst; // Main system reset
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input vid_ram_cfg_wr_i; // VID_RAMx_CFG Write strobe
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input vid_ram_cfg_wr_i; // VID_RAMx_CFG Write strobe
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input vid_ram_width_wr_i; // VID_RAMx_WIDTH Write strobe
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input vid_ram_width_wr_i; // VID_RAMx_WIDTH Write strobe
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`ifdef VRAM_BIGGER_4_KW
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input vid_ram_addr_hi_wr_i; // VID_RAMx_ADDR_HI Write strobe
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input vid_ram_addr_hi_wr_i; // VID_RAMx_ADDR_HI Write strobe
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`endif
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input vid_ram_addr_lo_wr_i; // VID_RAMx_ADDR_LO Write strobe
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input vid_ram_addr_lo_wr_i; // VID_RAMx_ADDR_LO Write strobe
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input vid_ram_data_wr_i; // VID_RAMx_DATA Write strobe
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input vid_ram_data_wr_i; // VID_RAMx_DATA Write strobe
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input vid_ram_data_rd_i; // VID_RAMx_DATA Read strobe
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input vid_ram_data_rd_i; // VID_RAMx_DATA Read strobe
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input dbg_freeze_i; // Freeze auto-increment on read when CPU stopped
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input dbg_freeze_i; // Freeze auto-increment on read when CPU stopped
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| Line 198... |
Line 194... |
// VID_RAMx_ADDR_HI Register
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// VID_RAMx_ADDR_HI Register
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//------------------------------------------------
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//------------------------------------------------
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wire [`APIX_MSB:0] vid_ram_addr;
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wire [`APIX_MSB:0] vid_ram_addr;
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wire [`APIX_MSB:0] vid_ram_addr_inc;
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wire [`APIX_MSB:0] vid_ram_addr_inc;
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wire vid_ram_addr_inc_wr;
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wire vid_ram_addr_inc_wr;
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reg vid_ram_addr_hi_wr_dly;
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`ifdef VRAM_BIGGER_4_KW
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`ifdef VRAM_BIGGER_4_KW
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reg [`APIX_HI_MSB:0] vid_ram_addr_hi;
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reg [`APIX_HI_MSB:0] vid_ram_addr_hi;
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always @ (posedge mclk or posedge puc_rst)
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always @ (posedge mclk or posedge puc_rst)
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| Line 215... |
Line 212... |
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//------------------------------------------------
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//------------------------------------------------
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// VID_RAMx_ADDR_LO Register
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// VID_RAMx_ADDR_LO Register
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//------------------------------------------------
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//------------------------------------------------
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reg [`APIX_LO_MSB:0] vid_ram_addr_lo;
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reg [`APIX_LO_MSB:0] vid_ram_addr_lo;
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reg vid_ram_addr_lo_wr_dly;
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always @ (posedge mclk or posedge puc_rst)
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) vid_ram_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
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if (puc_rst) vid_ram_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
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else if (vid_ram_addr_lo_wr_i) vid_ram_addr_lo <= per_din_i[`APIX_LO_MSB:0];
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else if (vid_ram_addr_lo_wr_i) vid_ram_addr_lo <= per_din_i[`APIX_LO_MSB:0];
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else if (vid_ram_addr_inc_wr) vid_ram_addr_lo <= vid_ram_addr_inc[`APIX_LO_MSB:0];
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else if (vid_ram_addr_inc_wr) vid_ram_addr_lo <= vid_ram_addr_inc[`APIX_LO_MSB:0];
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| Line 247... |
Line 243... |
.gfx_mode_2_bpp_i ( gfx_mode_2_bpp_i ), // Graphic mode 2 bpp resolution
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.gfx_mode_2_bpp_i ( gfx_mode_2_bpp_i ), // Graphic mode 2 bpp resolution
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.gfx_mode_4_bpp_i ( gfx_mode_4_bpp_i ), // Graphic mode 4 bpp resolution
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.gfx_mode_4_bpp_i ( gfx_mode_4_bpp_i ), // Graphic mode 4 bpp resolution
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.gfx_mode_8_bpp_i ( gfx_mode_8_bpp_i ), // Graphic mode 8 bpp resolution
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.gfx_mode_8_bpp_i ( gfx_mode_8_bpp_i ), // Graphic mode 8 bpp resolution
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.gfx_mode_16_bpp_i ( gfx_mode_16_bpp_i ), // Graphic mode 16 bpp resolution
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.gfx_mode_16_bpp_i ( gfx_mode_16_bpp_i ), // Graphic mode 16 bpp resolution
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.vid_ram_addr_i ( vid_ram_addr ), // Video-RAM address
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.vid_ram_addr_i ( vid_ram_addr ), // Video-RAM address
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.vid_ram_addr_init_i ( vid_ram_addr_lo_wr_dly ), // Video-RAM address initialization
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.vid_ram_addr_init_i ( vid_ram_addr_hi_wr_dly ), // Video-RAM address initialization
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.vid_ram_addr_step_i ( vid_ram_addr_inc_wr ), // Video-RAM address step
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.vid_ram_addr_step_i ( vid_ram_addr_inc_wr ), // Video-RAM address step
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.vid_ram_width_i ( vid_ram_width ), // Video-RAM width
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.vid_ram_width_i ( vid_ram_width ), // Video-RAM width
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.vid_ram_msk_mode_i ( vid_ram_msk_mode ), // Video-RAM Mask mode enable
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.vid_ram_msk_mode_i ( vid_ram_msk_mode ), // Video-RAM Mask mode enable
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.vid_ram_win_mode_i ( vid_ram_win_mode ), // Video-RAM Windows mode enable
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.vid_ram_win_mode_i ( vid_ram_win_mode ), // Video-RAM Windows mode enable
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.vid_ram_win_x_swap_i ( vid_ram_win_x_swap ), // Video-RAM X-Swap configuration
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.vid_ram_win_x_swap_i ( vid_ram_win_x_swap ), // Video-RAM X-Swap configuration
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| Line 330... |
Line 326... |
// VID_RAM0: Delay software read and write strobes
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// VID_RAM0: Delay software read and write strobes
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//--------------------------------------------------
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//--------------------------------------------------
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// Strobe writing to VID_RAMx_ADDR_LO register
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// Strobe writing to VID_RAMx_ADDR_LO register
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always @ (posedge mclk or posedge puc_rst)
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) vid_ram_addr_lo_wr_dly <= 1'b0;
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if (puc_rst) vid_ram_addr_hi_wr_dly <= 1'b0;
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else vid_ram_addr_lo_wr_dly <= vid_ram_addr_lo_wr_i;
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else vid_ram_addr_hi_wr_dly <= vid_ram_addr_hi_wr_i;
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// Strobe reading from VID_RAMx_DATA register
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// Strobe reading from VID_RAMx_DATA register
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reg vid_ram_data_rd_dly;
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reg vid_ram_data_rd_dly;
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always @ (posedge mclk or posedge puc_rst)
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) vid_ram_data_rd_dly <= 1'b0;
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if (puc_rst) vid_ram_data_rd_dly <= 1'b0;
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| Line 346... |
Line 342... |
always @ (posedge mclk or posedge puc_rst)
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) vid_ram_data_wr_dly <= 1'b0;
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if (puc_rst) vid_ram_data_wr_dly <= 1'b0;
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else vid_ram_data_wr_dly <= vid_ram_data_wr_i;
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else vid_ram_data_wr_dly <= vid_ram_data_wr_i;
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// Trigger read access after a write in MSK mode
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// Trigger read access after a write in MSK mode
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wire vid_ram_data_rd_msk = ((vid_ram_data_wr_dly | vid_ram_data_rd_dly | vid_ram_addr_lo_wr_i) & vid_ram_msk_mode & ~gfx_mode_16_bpp_i);
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wire vid_ram_data_rd_msk = ((vid_ram_data_wr_dly | vid_ram_data_rd_dly | vid_ram_addr_hi_wr_i) & vid_ram_msk_mode & ~gfx_mode_16_bpp_i);
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//------------------------------------------------
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//------------------------------------------------
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// Compute VIDEO-RAM Strobes & Data
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// Compute VIDEO-RAM Strobes & Data
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//------------------------------------------------
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//------------------------------------------------
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| Line 361... |
Line 357... |
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// Chip enable.
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// Chip enable.
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// Note: we perform a data read access:
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// Note: we perform a data read access:
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// - one cycle after a VID_RAM_DATA register read access (so that the address has been incremented)
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// - one cycle after a VID_RAM_DATA register read access (so that the address has been incremented)
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// - one cycle after a VID_RAM_ADDR_LO register write
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// - one cycle after a VID_RAM_ADDR_LO register write
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wire vid_ram_ce_early = (vid_ram_addr_lo_wr_i | vid_ram_data_rd_dly | vid_ram_data_rd_msk | // Read access
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wire vid_ram_ce_early = (vid_ram_addr_hi_wr_i | vid_ram_data_rd_dly | vid_ram_data_rd_msk | // Read access
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vid_ram_data_wr_i); // Write access
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vid_ram_data_wr_i); // Write access
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reg [1:0] vid_ram_ce;
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reg [1:0] vid_ram_ce;
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always @ (posedge mclk or posedge puc_rst)
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) vid_ram_ce <= 2'b00;
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if (puc_rst) vid_ram_ce <= 2'b00;
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| Line 384... |
Line 380... |
// Compute VIDEO-RAM Address
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// Compute VIDEO-RAM Address
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//------------------------------------------------
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//------------------------------------------------
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// Mux ram address for early read access when ADDR_LO is updated
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// Mux ram address for early read access when ADDR_LO is updated
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`ifdef VRAM_BIGGER_4_KW
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`ifdef VRAM_BIGGER_4_KW
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wire [`APIX_MSB:0] vid_ram_addr_mux = vid_ram_addr_lo_wr_i ? {vid_ram_addr[`APIX_MSB:16], per_din_i} :
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wire [`APIX_MSB:0] vid_ram_addr_mux = vid_ram_addr_hi_wr_i ? {per_din_i[`APIX_HI_MSB:0], vid_ram_addr[15:0]} :
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vid_ram_data_rd_msk ? vid_ram_addr_inc : vid_ram_addr;
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vid_ram_data_rd_msk ? vid_ram_addr_inc : vid_ram_addr;
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`else
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`else
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wire [`APIX_MSB:0] vid_ram_addr_mux = vid_ram_addr_lo_wr_i ? {per_din_i[`APIX_LO_MSB:0]} :
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wire [`APIX_MSB:0] vid_ram_addr_mux = vid_ram_addr_hi_wr_i ? {per_din_i[`APIX_LO_MSB:0]} :
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vid_ram_data_rd_msk ? vid_ram_addr_inc : vid_ram_addr;
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vid_ram_data_rd_msk ? vid_ram_addr_inc : vid_ram_addr;
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`endif
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`endif
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// Add frame pointer offset
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// Add frame pointer offset
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wire [`APIX_MSB:0] vid_ram_addr_offset = vid_ram_base_addr_i + vid_ram_addr_mux;
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wire [`APIX_MSB:0] vid_ram_addr_offset = vid_ram_base_addr_i + vid_ram_addr_mux;
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// Detect memory accesses for ADDR update
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// Detect memory accesses for ADDR update
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wire vid_ram_access_o = vid_ram_data_wr_i | vid_ram_data_rd_dly | vid_ram_addr_lo_wr_i | vid_ram_data_rd_msk;
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wire vid_ram_access_o = vid_ram_data_wr_i | vid_ram_data_rd_dly | vid_ram_addr_hi_wr_i | vid_ram_data_rd_msk;
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// Mux Address between the two interfaces
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// Mux Address between the two interfaces
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wire [`APIX_MSB:0] vid_ram_addr_nxt_o = {`APIX_MSB+1{vid_ram_access_o}} & vid_ram_addr_offset;
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wire [`APIX_MSB:0] vid_ram_addr_nxt_o = {`APIX_MSB+1{vid_ram_access_o}} & vid_ram_addr_offset;
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// Increment the address when accessing the VID_RAMx_DATA register:
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// Increment the address when accessing the VID_RAMx_DATA register:
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// - one clock cycle after a write access
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// - one clock cycle after a write access
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// - with the read access (if not in read-modify-write mode)
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// - with the read access (if not in read-modify-write mode)
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assign vid_ram_addr_inc_wr = vid_ram_addr_lo_wr_dly | vid_ram_data_wr_dly | (vid_ram_data_rd_i & ~dbg_freeze_i & ~vid_ram_rmw_mode);
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assign vid_ram_addr_inc_wr = vid_ram_addr_hi_wr_dly | vid_ram_data_wr_dly | (vid_ram_data_rd_i & ~dbg_freeze_i & ~vid_ram_rmw_mode);
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// Compute mask for the address LSBs depending on BPP resolution
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// Compute mask for the address LSBs depending on BPP resolution
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wire [3:0] gfx_mode_addr_msk = ( {4{gfx_mode_1_bpp_i}} | // Take 4 address LSBs in 1bpp mode
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wire [3:0] gfx_mode_addr_msk = ( {4{gfx_mode_1_bpp_i}} | // Take 4 address LSBs in 1bpp mode
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{1'b0, {3{gfx_mode_2_bpp_i}}} | // Take 3 address LSBs in 2bpp mode
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{1'b0, {3{gfx_mode_2_bpp_i}}} | // Take 3 address LSBs in 2bpp mode
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{2'b00, {2{gfx_mode_4_bpp_i}}} | // Take 2 address LSBs in 4bpp mode
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{2'b00, {2{gfx_mode_4_bpp_i}}} | // Take 2 address LSBs in 4bpp mode
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