| Line 46... |
Line 46... |
parameter FPW = 4,
|
parameter FPW = 4,
|
parameter DWIDTH = FPW*128,
|
parameter DWIDTH = FPW*128,
|
parameter LOG_NUM_LANES = 3,
|
parameter LOG_NUM_LANES = 3,
|
parameter NUM_LANES = 2**LOG_NUM_LANES,
|
parameter NUM_LANES = 2**LOG_NUM_LANES,
|
parameter HMC_PTR_SIZE = 8,
|
parameter HMC_PTR_SIZE = 8,
|
parameter HMC_RF_RWIDTH = 64,
|
parameter RF_COUNTER_SIZE = 64,
|
//Configure functionality
|
//Set Token Related
|
parameter LOG_MAX_RTC = 8,
|
parameter LOG_MAX_RX_TOKENS = 8,
|
|
parameter MAX_RTC_RET_LOG = 8,
|
|
//Control
|
|
parameter XIL_CNT_PIPELINED = 0,
|
parameter CTRL_LANE_POLARITY = 1,
|
parameter CTRL_LANE_POLARITY = 1,
|
|
parameter RX_RELAX_INIT_TIMING = 1,
|
|
parameter RX_BIT_SLIP_CNT_LOG = 5,
|
|
parameter DETECT_LANE_POLARITY = 1,
|
parameter CTRL_LANE_REVERSAL = 1,
|
parameter CTRL_LANE_REVERSAL = 1,
|
parameter BITSLIP_SHIFT_RIGHT= 1
|
parameter BITSLIP_SHIFT_RIGHT = 1,
|
|
parameter OPEN_RSP_MODE = 0
|
) (
|
) (
|
|
|
//----------------------------------
|
//----------------------------------
|
//----SYSTEM INTERFACE
|
//----SYSTEM INTERFACE
|
//----------------------------------
|
//----------------------------------
|
input wire clk,
|
input wire clk,
|
input wire res_n,
|
input wire res_n,
|
|
input wire run_rx,
|
|
|
//----------------------------------
|
//----------------------------------
|
//----TO HMC PHY
|
//----TO HMC PHY
|
//----------------------------------
|
//----------------------------------
|
input wire [DWIDTH-1:0] phy_scrambled_data_in,
|
input wire [DWIDTH-1:0] phy_scrambled_data_in,
|
output reg [NUM_LANES-1:0] init_bit_slip, //bit slip per lane
|
output reg [NUM_LANES-1:0] phy_bit_slip,
|
|
|
//----------------------------------
|
//----------------------------------
|
//----TO RX HTAX FIFO
|
//----TO RX HTAX FIFO
|
//----------------------------------
|
//----------------------------------
|
output reg [DWIDTH-1:0] d_out_fifo_data,
|
output wire [DWIDTH-1:0] d_out_fifo_data,
|
input wire d_out_fifo_full,
|
|
input wire d_out_fifo_a_full,
|
input wire d_out_fifo_a_full,
|
output reg d_out_fifo_shift_in,
|
output wire d_out_fifo_shift_in,
|
output reg [4*FPW-1:0] d_out_fifo_ctrl,
|
output wire [4*FPW-1:0] d_out_fifo_ctrl,
|
|
|
|
|
//----------------------------------
|
//----------------------------------
|
//----TO TX Block
|
//----TO TX Block
|
//----------------------------------
|
//----------------------------------
|
output reg tx_link_retry,
|
output reg tx_link_retry,
|
output reg tx_error_abort_mode,
|
output reg tx_error_abort_mode,
|
output reg tx_error_abort_mode_cleared,
|
output reg tx_error_abort_mode_cleared,
|
output reg [7:0] tx_hmc_frp,
|
output reg [7:0] tx_hmc_frp,
|
output reg [7:0] tx_rrp,
|
output reg [7:0] tx_rrp,
|
output reg [7:0] tx_returned_tokens,
|
output reg [MAX_RTC_RET_LOG-1:0] tx_returned_tokens,
|
output reg [LOG_FPW:0] tx_hmc_tokens_to_return,
|
output wire [LOG_FPW:0] tx_hmc_tokens_to_return,
|
output reg [LOG_FPW:0] tx_hmc_poisoned_tokens_to_return,
|
output wire [LOG_FPW:0] tx_hmc_poisoned_tokens_to_return,
|
|
|
//----------------------------------
|
//----------------------------------
|
//----RF
|
//----RF
|
//----------------------------------
|
//----------------------------------
|
//Monitoring 1-cycle set to increment
|
//Monitoring 1-cycle set to increment
|
output reg [HMC_RF_RWIDTH-1:0] rf_cnt_poisoned,
|
output wire [RF_COUNTER_SIZE-1:0] rf_cnt_poisoned,
|
output reg [HMC_RF_RWIDTH-1:0] rf_cnt_rsp,
|
output wire [RF_COUNTER_SIZE-1:0] rf_cnt_rsp,
|
//Status
|
//Status
|
output reg [1:0] rf_link_status,
|
output reg rf_link_up,
|
output reg [2:0] rf_hmc_init_status,
|
output reg [2:0] rf_rx_init_status,
|
input wire rf_tx_sends_ts1,
|
|
input wire rf_hmc_sleep,
|
input wire rf_hmc_sleep,
|
//Init Status
|
//Init Status
|
output wire [NUM_LANES-1:0] rf_descrambler_part_aligned,
|
output wire [NUM_LANES-1:0] rf_descrambler_part_aligned,
|
output wire [NUM_LANES-1:0] rf_descrambler_aligned,
|
output wire [NUM_LANES-1:0] rf_descrambler_aligned,
|
output wire rf_all_descramblers_aligned,
|
output wire rf_all_descramblers_aligned,
|
//Control
|
//Control
|
input wire [5:0] rf_bit_slip_time,
|
output wire [NUM_LANES-1:0] rf_lane_polarity,
|
input wire rf_hmc_init_cont_set,
|
|
output reg [NUM_LANES-1:0] rf_lane_polarity,
|
|
input wire rf_scrambler_disable,
|
input wire rf_scrambler_disable,
|
output reg rf_lane_reversal_detected,
|
output wire rf_lane_reversal_detected,
|
output reg [NUM_LANES-1:0] rf_descramblers_locked,
|
output reg [NUM_LANES-1:0] rf_descramblers_locked,
|
input wire [4:0] rf_irtry_received_threshold
|
input wire [4:0] rf_irtry_received_threshold
|
|
|
);
|
);
|
`include "hmc_field_functions.h"
|
`include "hmc_field_functions.h"
|
| Line 122... |
Line 125... |
//---------WIRING AND SIGNAL STUFF---------------------------------------------------------------------
|
//---------WIRING AND SIGNAL STUFF---------------------------------------------------------------------
|
//-----------------------------------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------------------------------
|
//=====================================================================================================
|
//=====================================================================================================
|
|
|
//------------------------------------------------------------------------------------Some general things
|
//------------------------------------------------------------------------------------Some general things
|
//Link state
|
//Link state -- Most likely will be encoded as one-hot FSM
|
localparam HMC_DOWN = 3'b000;
|
localparam HMC_DOWN = 3'b000;
|
localparam HMC_NULL = 3'b001;
|
localparam HMC_WAIT_FOR_NULL = 3'b001;
|
localparam HMC_TS1 = 3'b010;
|
localparam HMC_NULL = 3'b010;
|
localparam HMC_UP = 3'b100;
|
localparam HMC_TS1_PART_ALIGN = 3'b011;
|
|
localparam HMC_TS1_FIND_REF = 3'b100;
|
|
localparam HMC_TS1_ALIGN = 3'b101;
|
|
localparam HMC_NULL_NEXT = 3'b110;
|
|
localparam HMC_UP = 3'b111;
|
|
|
//Commands
|
//Commands
|
localparam CMD_IRTRY = 3'b011;
|
localparam CMD_IRTRY = 6'b000011;
|
localparam CMD_FLOW = 3'b000;
|
|
localparam CMD_RSP = 3'b111;
|
|
localparam CMD_RSP_ERROR = 6'b111110;
|
localparam CMD_RSP_ERROR = 6'b111110;
|
|
|
//Other helpful defines
|
//Other helpful defines
|
localparam WIDTH_PER_LANE = (DWIDTH/NUM_LANES);
|
localparam WIDTH_PER_LANE = (DWIDTH/NUM_LANES);
|
|
|
| Line 156... |
Line 161... |
reg [NUM_LANES-1:0] init_descrambler_aligned;
|
reg [NUM_LANES-1:0] init_descrambler_aligned;
|
assign rf_descrambler_part_aligned = init_descrambler_part_aligned;
|
assign rf_descrambler_part_aligned = init_descrambler_part_aligned;
|
assign rf_descrambler_aligned = init_descrambler_aligned;
|
assign rf_descrambler_aligned = init_descrambler_aligned;
|
|
|
//DATA and REORDERING
|
//DATA and REORDERING
|
reg [WIDTH_PER_LANE-1:0] init_data_per_lane [NUM_LANES-1:0];
|
|
wire [DWIDTH-1:0] init_d_in;
|
|
wire [128-1:0] init_d_in_flit [FPW-1:0];
|
wire [128-1:0] init_d_in_flit [FPW-1:0];
|
wire [WIDTH_PER_LANE-1:0] descrambled_data_per_lane [NUM_LANES-1:0];
|
wire [WIDTH_PER_LANE-1:0] descrambled_data_per_lane [NUM_LANES-1:0];
|
|
reg [WIDTH_PER_LANE-1:0] descrambled_data_per_lane_dly [NUM_LANES-1:0];
|
wire [DWIDTH-1:0] d_in;
|
wire [DWIDTH-1:0] d_in;
|
|
wire [DWIDTH-1:0] d_in_dly;
|
wire [128-1:0] d_in_flit [FPW-1:0];
|
wire [128-1:0] d_in_flit [FPW-1:0];
|
|
|
//Valid FLIT sources. A FLIT is valid when it is not NULL
|
//Valid FLIT sources. A FLIT is valid when it is not NULL
|
wire [FPW-1:0] valid_flit_src; //bit0 = flit0, ...
|
wire [FPW-1:0] valid_flit_src; //bit0 = flit0, ...
|
wire [FPW-1:0] init_valid_flit_src; //bit0 = flit0, ...
|
wire [FPW-1:0] init_valid_flit_src; //bit0 = flit0, ...
|
| Line 174... |
Line 179... |
//-- Apply lane reversal if detected
|
//-- Apply lane reversal if detected
|
for(n = 0; n < NUM_LANES; n = n + 1) begin : apply_lane_reversal
|
for(n = 0; n < NUM_LANES; n = n + 1) begin : apply_lane_reversal
|
for(w = 0; w < WIDTH_PER_LANE; w = w + 1) begin
|
for(w = 0; w < WIDTH_PER_LANE; w = w + 1) begin
|
if(CTRL_LANE_REVERSAL==1)begin
|
if(CTRL_LANE_REVERSAL==1)begin
|
assign d_in[w*NUM_LANES+n] = rf_lane_reversal_detected ? descrambled_data_per_lane[NUM_LANES-1-n][w] : descrambled_data_per_lane[n][w];
|
assign d_in[w*NUM_LANES+n] = rf_lane_reversal_detected ? descrambled_data_per_lane[NUM_LANES-1-n][w] : descrambled_data_per_lane[n][w];
|
assign init_d_in[w*NUM_LANES+n] = rf_lane_reversal_detected ? init_data_per_lane[NUM_LANES-1-n][w] : init_data_per_lane[n][w];
|
assign d_in_dly[w*NUM_LANES+n] = rf_lane_reversal_detected ? descrambled_data_per_lane_dly[NUM_LANES-1-n][w] : descrambled_data_per_lane_dly[n][w];
|
end else begin
|
end else begin
|
assign d_in[w*NUM_LANES+n] = descrambled_data_per_lane[n][w];
|
assign d_in[w*NUM_LANES+n] = descrambled_data_per_lane[n][w];
|
assign init_d_in[w*NUM_LANES+n] = init_data_per_lane[n][w];
|
assign d_in_dly[w*NUM_LANES+n] = descrambled_data_per_lane_dly[n][w];
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
|
|
for(f = 0; f < FPW; f = f + 1) begin : reorder_input_data
|
for(f = 0; f < FPW; f = f + 1) begin : reorder_input_data
|
//-- Reorder the descrambled data to FLITs
|
//-- Reorder the descrambled data to FLITs
|
assign d_in_flit[f] = d_in[128-1+(f*128):f*128];
|
assign d_in_flit[f] = d_in[128-1+(f*128):f*128];
|
assign init_d_in_flit[f] = init_d_in[128-1+(f*128):f*128];
|
assign init_d_in_flit[f] = d_in_dly[128-1+(f*128):f*128];
|
//-- Generate valid flit positions for the init sequence
|
//-- Generate valid flit positions
|
assign valid_flit_src[f] = (|d_in_flit[f] == 1'b0) ? 1'b0 : 1'b1;
|
assign valid_flit_src[f] = |d_in_flit[f][5:0];
|
assign init_valid_flit_src[f] = (|init_d_in_flit[f] == 1'b0) ? 1'b0 : 1'b1;
|
assign init_valid_flit_src[f] = |init_d_in_flit[f];
|
end
|
end
|
|
|
endgenerate
|
endgenerate
|
|
|
|
|
//------------------------------------------------------------------------------------INIT
|
//------------------------------------------------------------------------------------INIT
|
localparam LINK_DOWN = 2'b00;
|
localparam LINK_DOWN = 1'b0;
|
localparam LINK_INIT = 2'b01;
|
localparam LINK_UP = 1'b1;
|
localparam LINK_UP = 2'b10;
|
|
|
|
reg [5:0] init_bit_slip_cnt;
|
reg [NUM_LANES-1:0] init_bit_slip;
|
reg [4:0] init_wait_time;
|
reg [NUM_LANES-1:0] init_bit_slip_part;
|
|
reg [RX_BIT_SLIP_CNT_LOG-1:0]init_bit_slip_cnt;
|
wire [NUM_LANES-1:0] init_descrambler_locked; //locked from the descrambler
|
wire [NUM_LANES-1:0] init_descrambler_locked; //locked from the descrambler
|
wire link_is_up;
|
|
reg [3:0] init_tmp_seq;
|
reg [3:0] init_tmp_seq;
|
reg init_prbs_seen;
|
|
|
|
assign link_is_up = rf_link_status[1];
|
|
assign rf_all_descramblers_aligned = &init_descrambler_aligned;
|
assign rf_all_descramblers_aligned = &init_descrambler_aligned;
|
|
|
//--------------TS1 recognition
|
//--------------TS1 recognition
|
localparam ts1_independent_portion = {4'hF,4'h0};
|
localparam TS1_INDEPENDENT_PORTION = {4'hF,4'h0};
|
localparam ts1_lanex_portion = {4'h5};
|
localparam TS1_LANE0_PORTION = 4'h3; //Not used if RX_RELAX_INIT_TIMING==1
|
localparam ts1_lane7or15_portion = 4'hc;
|
localparam TS1_LANEX_PORTION = 4'h5; //Not used if RX_RELAX_INIT_TIMING==1
|
localparam ts1_lane0_portion = 4'h3;
|
localparam TS1_LANE7OR15_PORTION = 4'hc;
|
|
|
localparam ts1_per_cycle_and_lane = DWIDTH/NUM_LANES/16;
|
localparam TS1_SEQS_PER_CYCLE_AND_LANE = DWIDTH/NUM_LANES/16;
|
|
|
wire [NUM_LANES-1:0] init_lane_has_correct_ts1;
|
wire [NUM_LANES-1:0] init_lane_has_correct_ts1;
|
wire [ts1_per_cycle_and_lane-1:0] init_lane_has_correct_ts1_vec [NUM_LANES-1:0];
|
wire [TS1_SEQS_PER_CYCLE_AND_LANE-1:0]init_lane_has_correct_ts1_vec [NUM_LANES-1:0];
|
|
|
genvar t;
|
genvar t;
|
generate
|
generate
|
//Make sure that the lanes have valid ts1 sequences throughout the entire data stream
|
//Make sure that the lanes have valid ts1 sequences throughout the entire data stream
|
for(n=0;n<NUM_LANES;n=n+1) begin : lane_has_correct_ts1_gen
|
for(n=0;n<NUM_LANES;n=n+1) begin : lane_has_correct_ts1_gen
|
|
|
assign init_lane_has_correct_ts1[n] = &init_lane_has_correct_ts1_vec[n];
|
assign init_lane_has_correct_ts1[n] = &init_lane_has_correct_ts1_vec[n];
|
|
end
|
|
|
for(t=0;t<ts1_per_cycle_and_lane;t=t+1) begin
|
for(t=0;t<TS1_SEQS_PER_CYCLE_AND_LANE;t=t+1) begin : ts1_recognition_gen
|
if(n==0 || n==NUM_LANES-1) begin
|
if(RX_RELAX_INIT_TIMING==1) begin
|
assign init_lane_has_correct_ts1_vec[n][t] = (init_data_per_lane[n][(t*16)+16-1:(t*16)+4] == {ts1_independent_portion,ts1_lane7or15_portion})
|
for(n=0;n<NUM_LANES;n=n+1) begin
|
||
|
assign init_lane_has_correct_ts1_vec[n][t] = (descrambled_data_per_lane[n][(t*16)+8+:8] == {TS1_INDEPENDENT_PORTION});
|
(init_data_per_lane[n][(t*16)+16-1:(t*16)+4] == {ts1_independent_portion,ts1_lane0_portion});
|
|
end else begin
|
|
assign init_lane_has_correct_ts1_vec[n][t] = (init_data_per_lane[n][(t*16)+16-1:(t*16)+4] == {ts1_independent_portion,ts1_lanex_portion});
|
|
end
|
end
|
|
end else begin
|
|
for(n=1;n<NUM_LANES-1;n=n+1) begin
|
|
assign init_lane_has_correct_ts1_vec[n][t] = (descrambled_data_per_lane[n][(t*16)+4+:12] == {TS1_INDEPENDENT_PORTION,TS1_LANEX_PORTION});
|
|
end
|
|
assign init_lane_has_correct_ts1_vec[0][t] = (descrambled_data_per_lane[0][(t*16)+4+:12] == {TS1_INDEPENDENT_PORTION,TS1_LANE0_PORTION})||
|
|
(CTRL_LANE_REVERSAL==1 ? descrambled_data_per_lane[0][(t*16)+4+:12] == {TS1_INDEPENDENT_PORTION,TS1_LANE7OR15_PORTION} : 0);
|
|
assign init_lane_has_correct_ts1_vec[NUM_LANES-1][t] = (descrambled_data_per_lane[NUM_LANES-1][(t*16)+4+:12] == {TS1_INDEPENDENT_PORTION,TS1_LANE7OR15_PORTION})||
|
|
(CTRL_LANE_REVERSAL==1 ? descrambled_data_per_lane[NUM_LANES-1][(t*16)+4+:12] == {TS1_INDEPENDENT_PORTION,TS1_LANE0_PORTION} : 0);
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
//--------------Align the lanes, scan for the ts1 seq
|
//--------------Align the lanes, scan for the ts1 seq
|
reg [LOG_NUM_LANES-1:0] init_lane_cnt;
|
wire [LOG_NUM_LANES-1:0] init_lane_cnt;
|
|
assign init_lane_cnt = init_bit_slip_cnt[LOG_NUM_LANES-1:0];
|
wire [3:0] init_seq_diff;
|
wire [3:0] init_seq_diff;
|
|
|
//If one of the descramblers is already partially aligned search for other lanes with their ts1 sequence number close this lane.
|
//If one of the descramblers is already partially aligned search for other lanes with their ts1 sequence number close this lane.
|
assign init_seq_diff = |init_descrambler_part_aligned ?
|
assign init_seq_diff = (BITSLIP_SHIFT_RIGHT==1 ? (descrambled_data_per_lane[init_lane_cnt][3:0] - init_tmp_seq)
|
(BITSLIP_SHIFT_RIGHT==1 ? (init_data_per_lane[init_lane_cnt][3:0] - init_tmp_seq)
|
: init_tmp_seq - descrambled_data_per_lane[init_lane_cnt][3:0]);
|
: init_tmp_seq - init_data_per_lane[init_lane_cnt][3:0])
|
|
: 0;
|
|
|
|
//------------------------------------------------------------------------------------Input Stage: Scan for Packets, Headers, Tails ...
|
//------------------------------------------------------------------------------------Input Stage: Scan for Packets, Headers, Tails ...
|
reg [DWIDTH-1:0] data2crc;
|
|
reg [FPW-1:0] data2crc_hdr;
|
reg [FPW-1:0] data2crc_hdr;
|
reg [FPW-1:0] data2crc_tail;
|
reg [FPW-1:0] data2crc_tail;
|
reg [FPW-1:0] data2crc_valid;
|
reg [FPW-1:0] data2crc_valid;
|
wire [(FPW*4)-1:0] data2crc_lng;
|
wire [(FPW*4)-1:0] data2crc_lng;
|
reg [3:0] data2crc_lng_per_flit [FPW-1:0];
|
reg [3:0] data2crc_lng_per_flit [FPW-1:0];
|
| Line 266... |
Line 271... |
reg [FPW-1:0] data2crc_valid_comb;
|
reg [FPW-1:0] data2crc_valid_comb;
|
reg [3:0] data2crc_lng_per_flit_comb [FPW-1:0];
|
reg [3:0] data2crc_lng_per_flit_comb [FPW-1:0];
|
reg [3:0] data2crc_payload_remain_comb;
|
reg [3:0] data2crc_payload_remain_comb;
|
|
|
generate
|
generate
|
for(f = 0; f < (FPW); f = f + 1) begin
|
for(f = 0; f < (FPW); f = f + 1) begin : reorder_crc_input
|
assign data2crc_lng[(f*4)+4-1:(f*4)] = data2crc_lng_per_flit[f];
|
assign data2crc_lng[(f*4)+:4] = data2crc_lng_per_flit[f];
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
//------------------------------------------------------------------------------------CRC
|
//------------------------------------------------------------------------------------CRC
|
wire [DWIDTH-1:0] crc_d_out_data;
|
wire [DWIDTH-1:0] crc_d_out_data;
|
| Line 288... |
Line 293... |
for(f=0;f<FPW;f=f+1) begin : reorder_crc_output
|
for(f=0;f<FPW;f=f+1) begin : reorder_crc_output
|
assign crc_d_out_flit[f] = crc_d_out_data[128-1+(f*128):f*128];
|
assign crc_d_out_flit[f] = crc_d_out_data[128-1+(f*128):f*128];
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
//------------------------------------------------------------------------------------LNG and DLN stage
|
|
reg [128-1:0] flit_after_lng_check [FPW-1:0];
|
|
reg [FPW-1:0] flit_after_lng_check_is_hdr;
|
|
reg [FPW-1:0] flit_after_lng_check_is_tail;
|
|
reg [FPW-1:0] flit_after_lng_check_is_valid;
|
|
reg [FPW-1:0] flit_after_lng_check_is_error;
|
|
reg [FPW-1:0] flit_after_lng_check_is_poisoned;
|
|
reg [FPW-1:0] flit_after_lng_check_is_flow;
|
|
reg [FPW-1:0] flit_after_lng_check_has_rtc;
|
|
|
|
//------------------------------------------------------------------------------------Start TX retry Stage
|
//------------------------------------------------------------------------------------Start TX retry Stage
|
reg [128-1:0] flit_after_retry_stage [FPW-1:0];
|
reg [128-1:0] flit_after_irtry_stage [FPW-1:0];
|
reg [FPW-1:0] flit_after_retry_stage_is_hdr;
|
reg [FPW-1:0] flit_after_irtry_stage_is_hdr;
|
reg [FPW-1:0] flit_after_retry_stage_is_tail;
|
reg [FPW-1:0] flit_after_irtry_stage_is_tail;
|
reg [FPW-1:0] flit_after_retry_stage_is_valid;
|
reg [FPW-1:0] flit_after_irtry_stage_is_valid;
|
reg [FPW-1:0] flit_after_retry_stage_is_valid_mask_msb;
|
reg [FPW-1:0] flit_after_irtry_stage_is_error;
|
reg [FPW-1:0] flit_after_retry_stage_is_valid_mask_lsb;
|
reg [FPW-1:0] flit_after_irtry_stage_is_poisoned;
|
reg [FPW-1:0] flit_after_retry_stage_is_error;
|
reg [FPW-1:0] flit_after_irtry_stage_has_rtc;
|
reg [FPW-1:0] flit_after_retry_stage_is_poisoned;
|
reg [FPW-1:0] flit_after_irtry_stage_is_start_retry;
|
reg [FPW-1:0] flit_after_retry_stage_is_flow;
|
reg [FPW-1:0] flit_after_irtry_stage_is_clear_error;
|
reg [FPW-1:0] flit_after_retry_stage_has_rtc;
|
reg [FPW-1:0] flit_after_irtry_stage_is_start_retry_comb;
|
reg [FPW-1:0] flit_after_retry_stage_is_start_retry;
|
reg [FPW-1:0] flit_after_irtry_stage_is_clear_error_comb;
|
reg [FPW-1:0] flit_after_retry_stage_is_start_retry_comb;
|
|
|
|
//------------------------------------------------------------------------------------SeqStage and Seqnum
|
//------------------------------------------------------------------------------------SeqStage and Seqnum
|
reg [128-1:0] flit_after_seq_check [FPW-1:0];
|
reg [128-1:0] flit_after_seq_check [FPW-1:0];
|
reg [FPW-1:0] flit_after_seq_check_is_hdr;
|
reg [FPW-1:0] flit_after_seq_check_is_hdr;
|
reg [FPW-1:0] flit_after_seq_check_is_tail;
|
reg [FPW-1:0] flit_after_seq_check_is_tail;
|
reg [FPW-1:0] flit_after_seq_check_is_valid;
|
reg [FPW-1:0] flit_after_seq_check_is_valid;
|
reg [FPW-1:0] flit_after_seq_check_is_error;
|
reg [FPW-1:0] flit_after_seq_check_is_error;
|
reg [FPW-1:0] flit_after_seq_check_is_error_comb;
|
reg [FPW-1:0] flit_after_seq_check_is_error_comb;
|
reg [FPW-1:0] flit_after_seq_check_is_poisoned;
|
reg [FPW-1:0] flit_after_seq_check_is_poisoned;
|
reg [FPW-1:0] flit_after_seq_check_is_flow;
|
|
reg [FPW-1:0] flit_after_seq_check_has_rtc;
|
reg [FPW-1:0] flit_after_seq_check_has_rtc;
|
reg [FPW-1:0] flit_after_seq_check_is_start_retry;
|
reg [FPW-1:0] flit_after_seq_check_is_start_retry;
|
|
reg [FPW-1:0] flit_after_seq_check_is_clear_error;
|
|
|
reg [2:0] next_seqnum;
|
reg [2:0] next_seqnum;
|
reg [2:0] next_seqnum_comb; //use param instead
|
reg [2:0] next_seqnum_comb; //can be reduced to [1:0] for 2FLIT config
|
reg [2:0] first_seq_after_error;
|
reg [2:0] first_seq_after_error;
|
|
|
|
//------------------------------------------------------------------------------------IRTRY packet count stage
|
|
reg [128-1:0] flit_after_mask_stage [FPW-1:0];
|
|
reg [FPW-1:0] flit_after_mask_stage_is_hdr;
|
|
reg [FPW-1:0] flit_after_mask_stage_is_tail;
|
|
reg [FPW-1:0] flit_after_mask_stage_is_valid;
|
|
reg [FPW-1:0] flit_after_mask_stage_is_valid_mask_lsb;
|
|
reg [FPW-1:0] flit_after_mask_stage_is_valid_mask_msb;
|
|
reg [FPW-1:0] flit_after_mask_stage_is_error;
|
|
reg [FPW-1:0] flit_after_mask_stage_is_poisoned;
|
|
reg [FPW-1:0] flit_after_mask_stage_is_start_retry;
|
|
reg [FPW-1:0] flit_after_mask_stage_has_rtc;
|
|
|
|
|
|
//Assign FLITs to word, necessary for the invalidation stage pipeline
|
|
wire [DWIDTH-1:0] flit_after_mask_stage_word;
|
|
generate
|
|
for(f = 0; f < (FPW); f = f + 1) begin : reorder_flits_to_word
|
|
assign flit_after_mask_stage_word[(f*128)+128-1:(f*128)] = flit_after_mask_stage[f];
|
|
end
|
|
endgenerate
|
|
|
//------------------------------------------------------------------------------------Invalidation Stage
|
//------------------------------------------------------------------------------------Invalidation Stage
|
|
//Assuming Max Pkt size = 9 FLITs
|
localparam CYCLES_TO_COMPLETE_FULL_PACKET = (FPW == 2) ? 5 :
|
localparam CYCLES_TO_COMPLETE_FULL_PACKET = (FPW == 2) ? 5 :
|
(FPW == 4) ? 3 : //Assuming Max Pkt size = 9 FLITs
|
(FPW == 4) ? 3 :
|
(FPW == 6) ? 3 :
|
(FPW == 6) ? 3 :
|
(FPW == 8) ? 2 :
|
2;
|
1;
|
|
|
|
//Regs to retrieve the pkt length, assign the length to correspoding tail. The packet will be invalidated then
|
//Regs to retrieve the pkt length, assign the length to correspoding tail. The packet will be invalidated then
|
reg [3:0] lng_per_tail [FPW-1:0] ;
|
reg [3:0] lng_per_tail [FPW-1:0] ;
|
reg [3:0] lng_per_tail_comb [FPW-1:0] ;
|
reg [3:0] lng_per_tail_comb [FPW-1:0] ;
|
reg [3:0] lng_temp;
|
reg [3:0] lng_temp;
|
reg [3:0] lng_comb;
|
reg [3:0] lng_comb;
|
//Signal that an error was detected. Invalid all FLITs after
|
//Signal that an error was detected. Invalidate all FLITs after
|
reg error_detected;
|
reg error;
|
|
|
//Assign FLITs to word, necessary for the invalidation stage pipeline
|
|
wire [DWIDTH-1:0] flit_after_seq_check_word;
|
|
generate
|
|
for(f = 0; f < (FPW); f = f + 1) begin : reorder_flits_after_seq_to_word
|
|
assign flit_after_seq_check_word[(f*128)+128-1:(f*128)] = flit_after_seq_check[f];
|
|
end
|
|
endgenerate
|
|
|
|
reg [DWIDTH-1:0] flit_in_invalidation_data [CYCLES_TO_COMPLETE_FULL_PACKET-1:0];
|
reg [DWIDTH-1:0] flit_in_invalidation_data [CYCLES_TO_COMPLETE_FULL_PACKET-1:0];
|
reg [FPW-1:0] flit_in_invalidation_is_hdr [CYCLES_TO_COMPLETE_FULL_PACKET-1:0];
|
reg [FPW-1:0] flit_in_invalidation_is_hdr [CYCLES_TO_COMPLETE_FULL_PACKET-1:0];
|
reg [FPW-1:0] flit_in_invalidation_is_tail [CYCLES_TO_COMPLETE_FULL_PACKET-1:0];
|
reg [FPW-1:0] flit_in_invalidation_is_tail [CYCLES_TO_COMPLETE_FULL_PACKET-1:0];
|
reg [FPW-1:0] flit_in_invalidation_is_valid [CYCLES_TO_COMPLETE_FULL_PACKET-1:0];
|
reg [FPW-1:0] flit_in_invalidation_is_valid [CYCLES_TO_COMPLETE_FULL_PACKET-1:0];
|
reg [FPW-1:0] flit_in_invalidation_mask_error;
|
reg [FPW-1:0] flit_in_invalidation_mask_error;
|
reg [FPW-1:0] flit_in_invalidation_is_poisoned [CYCLES_TO_COMPLETE_FULL_PACKET-1:0];
|
reg [FPW-1:0] flit_in_invalidation_is_poisoned [CYCLES_TO_COMPLETE_FULL_PACKET-1:0];
|
reg [FPW-1:0] flit_in_invalidation0_is_poisoned_comb;
|
reg [FPW-1:0] flit_in_invalidation0_is_poisoned_comb;
|
reg [FPW-1:0] flit_in_invalidation_is_flow [CYCLES_TO_COMPLETE_FULL_PACKET-1:0];
|
|
reg [FPW-1:0] flit_in_invalidation_has_rtc [CYCLES_TO_COMPLETE_FULL_PACKET-1:0];
|
|
reg [FPW-1:0] flit_in_invalidation_is_start_retry[CYCLES_TO_COMPLETE_FULL_PACKET-1:0];
|
|
|
|
//------------------------------------------------------------------------------------Checked FLITs
|
//------------------------------------------------------------------------------------Checked FLITs
|
wire [128-1:0] checked_flit [FPW-1:0];
|
wire [128-1:0] checked_flit [FPW-1:0];
|
wire [FPW-1:0] checked_flit_is_poisoned;
|
wire [FPW-1:0] checked_flit_is_poisoned;
|
wire [FPW-1:0] checked_flit_is_valid;
|
wire [FPW-1:0] checked_flit_is_valid;
|
wire [FPW-1:0] checked_flit_is_hdr;
|
wire [FPW-1:0] checked_flit_is_hdr;
|
wire [FPW-1:0] checked_flit_is_tail;
|
wire [FPW-1:0] checked_flit_is_tail;
|
wire [FPW-1:0] checked_flit_has_rtc;
|
|
wire [FPW-1:0] checked_flit_is_flow;
|
|
wire [FPW-1:0] checked_flit_is_start_retry;
|
|
|
|
assign checked_flit_is_hdr = flit_in_invalidation_is_hdr [CYCLES_TO_COMPLETE_FULL_PACKET-1] & flit_in_invalidation_is_valid [CYCLES_TO_COMPLETE_FULL_PACKET-1];
|
assign checked_flit_is_hdr = flit_in_invalidation_is_hdr [CYCLES_TO_COMPLETE_FULL_PACKET-1] & flit_in_invalidation_is_valid [CYCLES_TO_COMPLETE_FULL_PACKET-1];
|
assign checked_flit_is_tail = flit_in_invalidation_is_tail [CYCLES_TO_COMPLETE_FULL_PACKET-1] & flit_in_invalidation_is_valid [CYCLES_TO_COMPLETE_FULL_PACKET-1];
|
assign checked_flit_is_tail = flit_in_invalidation_is_tail [CYCLES_TO_COMPLETE_FULL_PACKET-1] & flit_in_invalidation_is_valid [CYCLES_TO_COMPLETE_FULL_PACKET-1];
|
assign checked_flit_is_valid = flit_in_invalidation_is_valid [CYCLES_TO_COMPLETE_FULL_PACKET-1] ;
|
assign checked_flit_is_valid = flit_in_invalidation_is_valid [CYCLES_TO_COMPLETE_FULL_PACKET-1] ;
|
assign checked_flit_is_poisoned = flit_in_invalidation_is_poisoned [CYCLES_TO_COMPLETE_FULL_PACKET-1] & flit_in_invalidation_is_valid [CYCLES_TO_COMPLETE_FULL_PACKET-1];
|
assign checked_flit_is_poisoned = flit_in_invalidation_is_poisoned [CYCLES_TO_COMPLETE_FULL_PACKET-1] & flit_in_invalidation_is_valid [CYCLES_TO_COMPLETE_FULL_PACKET-1];
|
assign checked_flit_is_flow = flit_in_invalidation_is_flow [CYCLES_TO_COMPLETE_FULL_PACKET-1] & flit_in_invalidation_is_valid [CYCLES_TO_COMPLETE_FULL_PACKET-1];
|
|
assign checked_flit_has_rtc = flit_in_invalidation_has_rtc [CYCLES_TO_COMPLETE_FULL_PACKET-1] & flit_in_invalidation_is_valid [CYCLES_TO_COMPLETE_FULL_PACKET-1];
|
|
assign checked_flit_is_start_retry = flit_in_invalidation_is_start_retry[CYCLES_TO_COMPLETE_FULL_PACKET-1];
|
|
|
|
generate
|
generate
|
for(f = 0; f < (FPW); f = f + 1) begin : reorder_invalidation_word_back_to_flits
|
for(f = 0; f < (FPW); f = f + 1) begin : reorder_invalidation_word_back_to_flits
|
assign checked_flit[f] = flit_in_invalidation_data[CYCLES_TO_COMPLETE_FULL_PACKET-1][128-1+(f*128):f*128];
|
assign checked_flit[f] = flit_in_invalidation_data[CYCLES_TO_COMPLETE_FULL_PACKET-1][128-1+(f*128):f*128];
|
end
|
end
|
| Line 391... |
Line 389... |
//------------------------------------------------------------------------------------Counter
|
//------------------------------------------------------------------------------------Counter
|
reg [LOG_FPW:0] rf_cnt_poisoned_comb;
|
reg [LOG_FPW:0] rf_cnt_poisoned_comb;
|
reg [LOG_FPW:0] rf_cnt_rsp_comb;
|
reg [LOG_FPW:0] rf_cnt_rsp_comb;
|
|
|
//------------------------------------------------------------------------------------Input Buffer
|
//------------------------------------------------------------------------------------Input Buffer
|
reg [LOG_FPW:0] tokens_out_of_fifo_sum_comb;
|
reg [MAX_RTC_RET_LOG-1:0]rtc_sum_comb; //for 8 FLIT config, maximum 8*31 tokens will be returned per cycle
|
reg [LOG_FPW:0] tokens_poisoned;
|
|
reg [7:0] rtc_sum_comb; //for 8 FLIT config, maximum 8*31 tokens will be returned per cycle
|
|
|
|
reg [128-1:0] input_buffer_d_in_flit [FPW-1:0];
|
reg [128-1:0] input_buffer_d_in_flit [FPW-1:0];
|
reg [FPW-1:0] input_buffer_valid;
|
reg [FPW-1:0] input_buffer_is_valid;
|
reg [FPW-1:0] input_buffer_is_hdr;
|
reg [FPW-1:0] input_buffer_is_hdr;
|
reg [FPW-1:0] input_buffer_is_tail;
|
reg [FPW-1:0] input_buffer_is_tail;
|
reg [FPW-1:0] input_buffer_is_error_rsp;
|
reg [FPW-1:0] input_buffer_is_error_rsp;
|
wire [DWIDTH+(4*FPW)-1:0] input_buffer_d_in;
|
wire [DWIDTH+(4*FPW)-1:0] input_buffer_d_in;
|
wire [DWIDTH+(4*FPW)-1:0] input_buffer_d_out;
|
wire [DWIDTH+(4*FPW)-1:0] input_buffer_d_out;
|
wire input_buffer_empty;
|
wire input_buffer_empty;
|
reg input_buffer_shift_in;
|
wire input_buffer_shift_in;
|
wire input_buffer_shift_out;
|
wire input_buffer_shift_out;
|
assign input_buffer_shift_out = ~(input_buffer_empty || d_out_fifo_a_full);
|
assign input_buffer_shift_out = ~(input_buffer_empty || d_out_fifo_a_full);
|
|
|
generate
|
generate
|
for(f = 0; f < (FPW); f = f + 1) begin : assign_flits_to_input_buffer_to_a_single_reg
|
for(f = 0; f < (FPW); f = f + 1) begin : assign_flits_to_input_buffer_to_a_single_reg
|
assign input_buffer_d_in[f*128+128-1:f*128] = input_buffer_d_in_flit[f];
|
assign input_buffer_d_in[f*128+128-1:f*128] = input_buffer_d_in_flit[f];
|
assign input_buffer_d_in[DWIDTH+f] = input_buffer_valid[f];
|
assign input_buffer_d_in[DWIDTH+f] = input_buffer_is_valid[f];
|
assign input_buffer_d_in[DWIDTH+f+FPW] = input_buffer_is_hdr[f];
|
assign input_buffer_d_in[DWIDTH+f+FPW] = input_buffer_is_hdr[f];
|
assign input_buffer_d_in[DWIDTH+f+(2*FPW)] = input_buffer_is_tail[f];
|
assign input_buffer_d_in[DWIDTH+f+(2*FPW)] = input_buffer_is_tail[f];
|
assign input_buffer_d_in[DWIDTH+f+(3*FPW)] = input_buffer_is_error_rsp[f];
|
assign input_buffer_d_in[DWIDTH+f+(3*FPW)] = input_buffer_is_error_rsp[f];
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
//------------------------------------------------------------------------------------LINK RETRY
|
//------------------------------------------------------------------------------------LINK RETRY
|
reg [5:0] irtry_start_retry_cnt;
|
reg [4:0] irtry_start_retry_cnt;
|
reg [5:0] irtry_clear_error_cnt;
|
reg [4:0] irtry_clear_error_cnt;
|
reg [5:0] irtry_start_retry_cnt_comb;
|
reg [4:0] irtry_start_retry_cnt_comb;
|
reg [5:0] irtry_clear_error_cnt_comb;
|
reg [4:0] irtry_clear_error_cnt_comb;
|
reg irtry_clear_trig;
|
reg irtry_clear_trig;
|
reg irtry_clear_trig_comb;
|
|
|
|
//=====================================================================================================
|
//=====================================================================================================
|
//-----------------------------------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------------------------------
|
//---------ACTUAL LOGIC STARTS HERE--------------------------------------------------------------------
|
//---------ACTUAL LOGIC STARTS HERE--------------------------------------------------------------------
|
//-----------------------------------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------------------------------
|
//=====================================================================================================
|
//=====================================================================================================
|
|
|
//========================================================================================================================================
|
//========================================================================================================================================
|
//------------------------------------------------------------------INIT
|
//------------------------------------------------------------------INIT
|
//========================================================================================================================================
|
//========================================================================================================================================
|
always @(posedge clk) begin
|
|
|
generate
|
|
if(CTRL_LANE_REVERSAL==1) begin : control_lane_reversal
|
|
reg init_lane_reversal_detected;
|
|
assign rf_lane_reversal_detected = init_lane_reversal_detected;
|
|
|
|
`ifdef ASYNC_RES
|
|
always @(posedge clk or negedge res_n) begin `else
|
|
always @(posedge clk) begin `endif
|
|
if(!res_n) begin
|
|
init_lane_reversal_detected <= 1'b0;
|
|
end else begin
|
|
if(rf_rx_init_status==HMC_DOWN) begin
|
|
init_lane_reversal_detected <= 1'b0;
|
|
end
|
|
if(rf_rx_init_status==HMC_TS1_ALIGN && rf_all_descramblers_aligned && (descrambled_data_per_lane[0][7:4] == TS1_LANE7OR15_PORTION)) begin
|
|
//lane reversal detected, reverse the input stream lane by lane
|
|
init_lane_reversal_detected <= 1'b1;
|
|
end
|
|
end
|
|
end
|
|
end else begin
|
|
assign rf_lane_reversal_detected = 1'b0;
|
|
end
|
|
|
|
if(DETECT_LANE_POLARITY==1) begin : detect_lane_reversal
|
|
reg [NUM_LANES-1:0] init_lane_polarity;
|
|
assign rf_lane_polarity = init_lane_polarity;
|
|
`ifdef ASYNC_RES
|
|
always @(posedge clk or negedge res_n) begin `else
|
|
always @(posedge clk) begin `endif
|
|
if(!res_n) begin
|
|
init_lane_polarity <= {NUM_LANES{1'b0}};
|
|
end else begin
|
|
if(rf_rx_init_status==HMC_DOWN) begin
|
|
init_lane_polarity <= {NUM_LANES{1'b0}};
|
|
end
|
|
//Detect Lane polarity when HMC is sending first NULLs
|
|
if(rf_rx_init_status==HMC_WAIT_FOR_NULL) begin
|
for(i_l = 0;i_l<NUM_LANES;i_l=i_l+1)begin
|
for(i_l = 0;i_l<NUM_LANES;i_l=i_l+1)begin
|
init_data_per_lane[i_l] <= descrambled_data_per_lane[i_l];
|
if(descrambled_data_per_lane[i_l] == {WIDTH_PER_LANE{1'b1}})begin
|
|
init_lane_polarity[i_l] <= 1'b1;
|
|
end
|
end
|
end
|
end
|
end
|
|
end
|
|
end
|
|
end else begin
|
|
assign rf_lane_polarity = {NUM_LANES{1'b0}};
|
|
end
|
|
endgenerate
|
|
|
`ifdef ASYNC_RES
|
`ifdef ASYNC_RES
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk) begin `endif
|
always @(posedge clk) begin `endif
|
|
|
|
for(i_l = 0;i_l<NUM_LANES;i_l=i_l+1)begin
|
|
`ifdef RESET_ALL
|
|
if(!res_n) descrambled_data_per_lane_dly[i_l] <= {WIDTH_PER_LANE{1'b0}};
|
|
else
|
|
`endif
|
|
descrambled_data_per_lane_dly[i_l] <= descrambled_data_per_lane[i_l];
|
|
end
|
|
|
if(!res_n) begin
|
if(!res_n) begin
|
//----Misc
|
//----Misc
|
init_descrambler_aligned <= {NUM_LANES{1'b0}};
|
init_descrambler_aligned <= {NUM_LANES{1'b0}};
|
init_descrambler_part_aligned <= {NUM_LANES{1'b0}};
|
init_descrambler_part_aligned <= {NUM_LANES{1'b0}};
|
|
phy_bit_slip <= {NUM_LANES{1'b0}};
|
init_bit_slip <= {NUM_LANES{1'b0}};
|
init_bit_slip <= {NUM_LANES{1'b0}};
|
init_bit_slip_cnt <= 6'h0;
|
init_bit_slip_part <= {NUM_LANES{1'b0}};
|
init_wait_time <= 5'h0;
|
init_bit_slip_cnt <= {RX_BIT_SLIP_CNT_LOG{1'b0}};
|
init_tmp_seq <= 4'h0;
|
init_tmp_seq <= 4'h0;
|
init_lane_cnt <= {LOG_NUM_LANES{1'b0}};
|
rf_rx_init_status <= HMC_DOWN;
|
init_prbs_seen <= 1'b0;
|
rf_link_up <= LINK_DOWN;
|
rf_hmc_init_status <= HMC_DOWN;
|
|
rf_link_status <= LINK_DOWN;
|
|
rf_lane_polarity <= {NUM_LANES{1'b0}};
|
|
rf_lane_reversal_detected <= 1'b0;
|
|
rf_descramblers_locked <= {NUM_LANES{1'b0}};
|
rf_descramblers_locked <= {NUM_LANES{1'b0}};
|
|
|
end
|
end
|
else begin
|
else begin
|
|
|
rf_descramblers_locked <= init_descrambler_locked;
|
rf_descramblers_locked <= run_rx ? init_descrambler_locked : {NUM_LANES{1'b0}};
|
init_bit_slip <= {NUM_LANES{1'b0}};
|
init_bit_slip <= {NUM_LANES{1'b0}};
|
|
init_bit_slip_part <= {NUM_LANES{1'b0}};
|
|
phy_bit_slip <= init_bit_slip | init_bit_slip_part;
|
|
init_tmp_seq <= init_tmp_seq + INIT_SEQ_INC_PER_CYCLE;
|
|
|
|
init_bit_slip_cnt <= init_bit_slip_cnt +1;
|
|
|
if(rf_hmc_sleep || !rf_hmc_init_cont_set) begin
|
case (rf_rx_init_status)
|
rf_link_status <= LINK_DOWN;
|
HMC_DOWN: begin
|
end else if(rf_link_status == LINK_DOWN) begin
|
|
//Begin (Re-)Init
|
|
init_descrambler_aligned <= {NUM_LANES{1'b0}};
|
init_descrambler_aligned <= {NUM_LANES{1'b0}};
|
init_descrambler_part_aligned <= {NUM_LANES{1'b0}};
|
init_descrambler_part_aligned <= {NUM_LANES{1'b0}};
|
init_wait_time <= 5'h1f;
|
if(&rf_descramblers_locked) begin
|
init_tmp_seq <= 4'h0;
|
rf_rx_init_status <= HMC_WAIT_FOR_NULL;
|
init_lane_cnt <= {LOG_NUM_LANES{1'b0}};
|
|
init_prbs_seen <= 1'b0;
|
|
rf_hmc_init_status <= HMC_DOWN;
|
|
rf_link_status <= LINK_INIT;
|
|
rf_lane_polarity <= {NUM_LANES{1'b0}};
|
|
rf_lane_reversal_detected <= 1'b0;
|
|
rf_descramblers_locked <= {NUM_LANES{1'b0}};
|
|
end
|
end
|
|
|
//Detect Lane polarity when HMC is sending first NULLs
|
|
if(&rf_descramblers_locked && rf_link_status == LINK_INIT) begin
|
|
for(i_l = 0;i_l<NUM_LANES;i_l=i_l+1)begin
|
|
if(init_data_per_lane[i_l] == {WIDTH_PER_LANE{1'b1}})begin
|
|
rf_lane_polarity[i_l] <= 1'b1;
|
|
end
|
end
|
|
HMC_WAIT_FOR_NULL: begin
|
|
if(|init_valid_flit_src == 1'b0) begin
|
|
rf_rx_init_status <= HMC_NULL;
|
end
|
end
|
end
|
end
|
|
HMC_NULL: begin
|
if(rf_hmc_init_status == HMC_DOWN) begin
|
if(&init_valid_flit_src) begin
|
if(|init_valid_flit_src) begin
|
rf_rx_init_status <= HMC_TS1_PART_ALIGN;
|
init_prbs_seen <= 1'b1;
|
|
end
|
end
|
if(!init_valid_flit_src && init_prbs_seen && &rf_descramblers_locked) begin
|
|
rf_hmc_init_status <= HMC_NULL;
|
|
end
|
end
|
|
HMC_TS1_PART_ALIGN: begin
|
|
if(|init_bit_slip_cnt[RX_BIT_SLIP_CNT_LOG-1:LOG_NUM_LANES] == 1'b0)begin
|
|
init_bit_slip_part[init_lane_cnt] <= ~init_lane_has_correct_ts1[init_lane_cnt];
|
|
init_descrambler_part_aligned[init_lane_cnt] <= init_lane_has_correct_ts1[init_lane_cnt];
|
end
|
end
|
|
if(&init_descrambler_part_aligned/*=={NUM_LANES{1'b1}}*/) begin
|
//When TX block sends ts1, start init process
|
rf_rx_init_status <= HMC_TS1_FIND_REF;
|
if(rf_tx_sends_ts1 && &init_valid_flit_src) begin
|
init_tmp_seq <= descrambled_data_per_lane[0][3:0] + INIT_SEQ_INC_PER_CYCLE;
|
rf_hmc_init_status <= HMC_TS1;
|
init_bit_slip_cnt <= {RX_BIT_SLIP_CNT_LOG{1'b0}};
|
end
|
end
|
|
end
|
|
HMC_TS1_FIND_REF: begin
|
|
if(init_seq_diff < 2)
|
|
init_tmp_seq <= descrambled_data_per_lane[init_lane_cnt][3:0] + INIT_SEQ_INC_PER_CYCLE;
|
|
|
if(rf_hmc_init_status==HMC_TS1) begin
|
if(&init_bit_slip_cnt==1'b1)
|
// -------------------------------------------------------------------------TS1 AND DESCRAMBLER SYNCHRONIZATION
|
rf_rx_init_status <= HMC_TS1_ALIGN;
|
if(!rf_all_descramblers_aligned) begin // repeat this until all descramblers are aligned !!
|
|
|
|
if(|init_wait_time == 1'b0)begin
|
|
|
|
init_tmp_seq <= init_tmp_seq + INIT_SEQ_INC_PER_CYCLE;
|
|
|
|
if(|init_bit_slip_cnt == 1'b0)begin
|
|
|
|
init_lane_cnt <= init_lane_cnt + 1;
|
|
|
|
if(!init_descrambler_part_aligned[init_lane_cnt])begin
|
|
init_bit_slip[init_lane_cnt] <= ~init_lane_has_correct_ts1[init_lane_cnt];
|
|
//if the current lane is more advanced than the current reference lane, set this lane as new reference
|
|
if(init_seq_diff < 2 && init_lane_has_correct_ts1[init_lane_cnt]) begin
|
|
init_tmp_seq <= init_data_per_lane[init_lane_cnt][3:0] + INIT_SEQ_INC_PER_CYCLE;
|
|
end
|
|
end
|
end
|
|
HMC_TS1_ALIGN: begin
|
|
|
if(&init_descrambler_part_aligned) begin
|
if(|init_bit_slip_cnt[RX_BIT_SLIP_CNT_LOG-1:LOG_NUM_LANES] == 1'b0)begin
|
if(|init_seq_diff==1'b0 && init_lane_has_correct_ts1[init_lane_cnt])begin
|
if(|init_seq_diff==1'b0 && init_lane_has_correct_ts1[init_lane_cnt])begin
|
init_descrambler_aligned[init_lane_cnt] <= 1'b1;
|
init_descrambler_aligned[init_lane_cnt] <= 1'b1;
|
end else begin
|
end else begin
|
init_bit_slip[init_lane_cnt] <= 1'b1;
|
init_bit_slip[init_lane_cnt] <= 1'b1;
|
end
|
end
|
end else begin
|
|
init_descrambler_part_aligned[init_lane_cnt] <= init_lane_has_correct_ts1[init_lane_cnt];
|
|
end
|
end
|
|
|
if(init_lane_cnt == NUM_LANES-1)begin
|
if(rf_all_descramblers_aligned) begin
|
init_bit_slip_cnt <= rf_bit_slip_time;
|
rf_rx_init_status <= HMC_NULL_NEXT;
|
end
|
end
|
|
|
end else begin
|
|
init_bit_slip_cnt <= init_bit_slip_cnt -1;
|
|
end
|
end
|
|
HMC_NULL_NEXT: begin
|
end else begin
|
if(|init_valid_flit_src == 1'b0) begin
|
init_wait_time <= init_wait_time -1;
|
rf_rx_init_status <= HMC_UP;
|
|
rf_link_up <= LINK_UP;
|
end
|
end
|
// -------------------------------------------------------------------------SECOND NULL SEQUENCE
|
|
end else begin // now that all is synchronized continue with NULL and TRET
|
|
|
|
//lane reversal detected, reverse the input stream lane by lane
|
|
if(init_data_per_lane[0][7:4] == ts1_lane7or15_portion)begin
|
|
rf_lane_reversal_detected <= 1'b1;
|
|
end
|
end
|
|
|
//when received NULLs again, init done (initial TRETs are treated as normal packets)
|
HMC_UP: begin
|
if(|init_valid_flit_src == 1'b0)begin
|
if(rf_hmc_sleep || !run_rx) begin
|
rf_link_status <= LINK_UP;
|
rf_rx_init_status <= HMC_DOWN;
|
rf_hmc_init_status <= HMC_UP;
|
rf_link_up <= LINK_DOWN;
|
end
|
|
end
|
end
|
end
|
end
|
|
endcase
|
end
|
end
|
end
|
end
|
|
|
//========================================================================================================================================
|
//========================================================================================================================================
|
//------------------------------------------------------------------Packet Processing
|
//------------------------------------------------------------------Packet Processing
|
| Line 580... |
Line 601... |
data2crc_tail_comb = {FPW{1'b0}};
|
data2crc_tail_comb = {FPW{1'b0}};
|
data2crc_valid_comb = {FPW{1'b0}};
|
data2crc_valid_comb = {FPW{1'b0}};
|
|
|
for(i_f=0;i_f<FPW;i_f=i_f+1) begin
|
for(i_f=0;i_f<FPW;i_f=i_f+1) begin
|
|
|
data2crc_lng_per_flit_comb[i_f] = {128{1'b0}};
|
data2crc_lng_per_flit_comb[i_f] = 4'h0;
|
|
|
if(data2crc_payload_remain_comb ==4'h1) begin
|
|
data2crc_tail_comb[i_f] = 1'b1;
|
|
end
|
|
|
|
if(data2crc_payload_remain_comb) begin
|
case (data2crc_payload_remain_comb)
|
|
4'h1: begin
|
|
data2crc_tail_comb[i_f] = 1'b1;
|
data2crc_valid_comb[i_f] = 1'b1;
|
data2crc_valid_comb[i_f] = 1'b1;
|
data2crc_payload_remain_comb = data2crc_payload_remain_comb - 1;
|
data2crc_payload_remain_comb = 4'h0;
|
end else if(valid_flit_src[i_f])begin
|
end
|
|
4'h0: begin
|
|
if(valid_flit_src[i_f])begin
|
data2crc_hdr_comb[i_f] = 1'b1;
|
data2crc_hdr_comb[i_f] = 1'b1;
|
data2crc_valid_comb[i_f] = 1'b1;
|
data2crc_valid_comb[i_f] = 1'b1;
|
|
if(lng(d_in_flit[i_f])<2 || lng(d_in_flit[i_f])>9 || !lng_dln_equal(d_in_flit[i_f]))begin
|
if(lng(d_in_flit[i_f]) < 2 || lng(d_in_flit[i_f]) > 9) begin
|
data2crc_lng_per_flit_comb[i_f] = 4'h1;
|
//Treat false lng values as single FLIT packets which will force error abort mode
|
|
data2crc_tail_comb[i_f] = 1'b1;
|
data2crc_tail_comb[i_f] = 1'b1;
|
data2crc_lng_per_flit_comb[i_f] = 1;
|
data2crc_payload_remain_comb = 4'h0;
|
end else begin
|
end else begin
|
data2crc_payload_remain_comb = lng(d_in_flit[i_f]) -1;
|
data2crc_payload_remain_comb = lng(d_in_flit[i_f]) -1;
|
data2crc_lng_per_flit_comb[i_f] = lng(d_in_flit[i_f]);
|
data2crc_lng_per_flit_comb[i_f] = lng(d_in_flit[i_f]);
|
end
|
end
|
end
|
end
|
|
end
|
|
default: begin
|
|
data2crc_valid_comb[i_f] = 1'b1;
|
|
data2crc_payload_remain_comb = data2crc_payload_remain_comb - 1;
|
|
end
|
|
endcase
|
end
|
end
|
end
|
end
|
|
|
//Register the combinational logic from previous stage
|
//Register the combinational logic from previous stage
|
`ifdef ASYNC_RES
|
`ifdef ASYNC_RES
|
| Line 616... |
Line 641... |
if(!res_n) begin
|
if(!res_n) begin
|
|
|
data2crc_hdr <= {FPW{1'b0}};
|
data2crc_hdr <= {FPW{1'b0}};
|
data2crc_tail <= {FPW{1'b0}};
|
data2crc_tail <= {FPW{1'b0}};
|
data2crc_valid <= {FPW{1'b0}};
|
data2crc_valid <= {FPW{1'b0}};
|
|
data2crc_payload_remain <= 4'h0;
|
data2crc_payload_remain <= {4{1'b0}};
|
|
|
|
for(i_f=0;i_f<FPW;i_f=i_f+1) begin
|
for(i_f=0;i_f<FPW;i_f=i_f+1) begin
|
data2crc_lng_per_flit[i_f] <= {128{1'b0}};
|
data2crc_lng_per_flit[i_f] <= 4'h0;
|
end
|
end
|
|
|
data2crc <= {DWIDTH{1'b0}};
|
|
|
|
end else begin
|
end else begin
|
if(link_is_up) begin
|
if(rf_link_up) begin
|
data2crc_hdr <= data2crc_hdr_comb;
|
|
data2crc_tail <= data2crc_tail_comb;
|
|
data2crc_valid <= data2crc_valid_comb;
|
data2crc_valid <= data2crc_valid_comb;
|
end
|
end
|
|
|
|
data2crc_hdr <= data2crc_hdr_comb;
|
|
data2crc_tail <= data2crc_tail_comb;
|
data2crc_payload_remain <= data2crc_payload_remain_comb;
|
data2crc_payload_remain <= data2crc_payload_remain_comb;
|
|
|
for(i_f=0;i_f<FPW;i_f=i_f+1) begin
|
for(i_f=0;i_f<FPW;i_f=i_f+1) begin
|
data2crc_lng_per_flit[i_f] <= data2crc_lng_per_flit_comb[i_f];
|
data2crc_lng_per_flit[i_f] <= data2crc_lng_per_flit_comb[i_f];
|
end
|
end
|
|
|
data2crc <= d_in;
|
|
|
|
end
|
|
end
|
|
|
|
//==================================================================================
|
|
//---------------------------------LNG/DLN check
|
|
//==================================================================================
|
|
`ifdef ASYNC_RES
|
|
always @(posedge clk or negedge res_n) begin `else
|
|
always @(posedge clk) begin `endif
|
|
if(!res_n) begin
|
|
|
|
flit_after_lng_check_is_hdr <= {FPW{1'b0}};
|
|
flit_after_lng_check_is_tail <= {FPW{1'b0}};
|
|
flit_after_lng_check_is_valid <= {FPW{1'b0}};
|
|
flit_after_lng_check_is_poisoned <= {FPW{1'b0}};
|
|
flit_after_lng_check_is_flow <= {FPW{1'b0}};
|
|
flit_after_lng_check_has_rtc <= {FPW{1'b0}};
|
|
flit_after_lng_check_is_error <= {FPW{1'b0}};
|
|
|
|
for(i_f = 0; i_f < FPW; i_f = i_f + 1) begin
|
|
flit_after_lng_check[i_f] <= {128{1'b0}};
|
|
end
|
|
|
|
end else begin
|
|
flit_after_lng_check_is_hdr <= crc_d_out_flit_is_hdr;
|
|
flit_after_lng_check_is_tail <= crc_d_out_flit_is_tail;
|
|
flit_after_lng_check_is_valid <= crc_d_out_flit_is_valid;
|
|
flit_after_lng_check_is_poisoned <= crc_d_out_flit_is_poisoned;
|
|
flit_after_lng_check_is_flow <= crc_d_out_flit_is_flow;
|
|
flit_after_lng_check_has_rtc <= crc_d_out_flit_has_rtc;
|
|
flit_after_lng_check_is_error <= crc_d_out_flit_is_error;
|
|
|
|
for(i_f = 0; i_f < FPW; i_f = i_f + 1) begin
|
|
flit_after_lng_check[i_f] <= crc_d_out_flit[i_f];
|
|
end
|
|
|
|
//perform lng/dln check
|
|
for(i_f = 0; i_f < FPW; i_f = i_f + 1) begin
|
|
if(crc_d_out_flit_is_hdr[i_f] && (lng(crc_d_out_flit[i_f]) != dln(crc_d_out_flit[i_f]))) begin
|
|
flit_after_lng_check_is_error[i_f] <= 1'b1;
|
|
end
|
|
end
|
|
end
|
end
|
end
|
end
|
|
|
//====================================================================
|
//====================================================================
|
//---------------------------------Start Retry Stage
|
//---------------------------------IRTRY Stage
|
//====================================================================
|
//====================================================================
|
//-- Count all types of IRTRY packets
|
//-- Count all types of IRTRY packets
|
always @(*) begin
|
always @(*) begin
|
|
|
//Set the lower bit mask for the next stage: Mask out all error FLITs
|
flit_after_irtry_stage_is_start_retry_comb = {FPW{1'b0}};
|
flit_after_retry_stage_is_valid_mask_lsb = {FPW{1'b1}};
|
flit_after_irtry_stage_is_clear_error_comb = {FPW{1'b0}};
|
for(i_f = FPW-1; i_f >=0; i_f = i_f - 1) begin
|
|
if(flit_after_lng_check_is_error[i_f])begin
|
|
//Pass the tail in case it is an crc error so that the corresponding FLITs of the packet can be invalidated
|
|
//but mask out single flit packets!
|
|
flit_after_retry_stage_is_valid_mask_lsb = {FPW{1'b1}} >> (FPW-i_f-(flit_after_lng_check_is_tail[i_f] & !flit_after_lng_check_is_hdr[i_f]));
|
|
end
|
|
end
|
|
|
|
//Next up, count both types of irtry packets and set the mask accordingly for irtry start packets in error abort mode and the
|
|
//final clear abort FLIT that reaches the threshold
|
|
|
|
flit_after_retry_stage_is_start_retry_comb = {FPW{1'b0}};
|
|
|
|
if( (tx_error_abort_mode && !irtry_clear_trig) ||
|
|
|(flit_after_retry_stage_is_error) ||
|
|
|(flit_after_seq_check_is_error)
|
|
)begin
|
|
flit_after_retry_stage_is_valid_mask_msb = {FPW{1'b0}};
|
|
end else begin
|
|
flit_after_retry_stage_is_valid_mask_msb = {FPW{1'b1}};
|
|
end
|
|
|
|
irtry_clear_trig_comb = 1'b0;
|
|
|
|
irtry_clear_error_cnt_comb = irtry_clear_error_cnt;
|
irtry_clear_error_cnt_comb = irtry_clear_error_cnt;
|
irtry_start_retry_cnt_comb = irtry_start_retry_cnt;
|
irtry_start_retry_cnt_comb = irtry_start_retry_cnt;
|
|
|
|
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
|
|
if( flit_after_lng_check_is_flow[i_f] &&
|
if( crc_d_out_flit_is_flow[i_f] &&
|
cmd(flit_after_lng_check[i_f]) == {CMD_FLOW,CMD_IRTRY} &&
|
cmd(crc_d_out_flit[i_f]) == {CMD_IRTRY} &&
|
!flit_after_lng_check_is_error[i_f]
|
!crc_d_out_flit_is_error[i_f]
|
) begin
|
) begin
|
|
|
if(irtry_start_retry_flag(flit_after_lng_check[i_f])) begin
|
if(irtry_start_retry_flag(crc_d_out_flit[i_f])) begin
|
//it's a start tx retry pkt
|
//it's a start tx retry pkt
|
irtry_start_retry_cnt_comb = irtry_start_retry_cnt_comb + 6'h1;
|
irtry_start_retry_cnt_comb = irtry_start_retry_cnt_comb + 5'h1;
|
irtry_clear_error_cnt_comb = 6'h0;
|
irtry_clear_error_cnt_comb = 5'h0;
|
end else begin
|
end else begin
|
//must be clear error pkt
|
//must be clear error pkt
|
irtry_clear_error_cnt_comb = irtry_clear_error_cnt_comb + 6'h1;
|
irtry_clear_error_cnt_comb = irtry_clear_error_cnt_comb + 5'h1;
|
irtry_start_retry_cnt_comb = 6'h0;
|
irtry_start_retry_cnt_comb = 5'h0;
|
end
|
end
|
|
|
if(irtry_start_retry_cnt_comb == rf_irtry_received_threshold) begin
|
if(irtry_start_retry_cnt_comb == rf_irtry_received_threshold) begin
|
//The start retry packet that reaches the trehold is treated as valid and will trigger tx retry
|
//The start retry packet that reaches the trehold is treated as valid and will trigger tx retry
|
flit_after_retry_stage_is_valid_mask_msb[i_f] = 1'b1;
|
flit_after_irtry_stage_is_start_retry_comb[i_f] = 1'b1;
|
flit_after_retry_stage_is_start_retry_comb[i_f] = 1'b1;
|
|
end
|
end
|
|
|
//Clear error abort when threshold reached, allow following FLITs to be valid
|
//Clear error abort when threshold reached, allow following FLITs to be valid
|
if(irtry_clear_error_cnt_comb == rf_irtry_received_threshold) begin
|
if(irtry_clear_error_cnt_comb == rf_irtry_received_threshold) begin
|
irtry_clear_trig_comb = 1'b1;
|
flit_after_irtry_stage_is_clear_error_comb[i_f] = 1'b1;
|
flit_after_retry_stage_is_valid_mask_msb = {FPW{1'b1}} << (i_f);
|
|
end
|
end
|
|
|
end else begin
|
end else begin
|
//Reset both counters when received a non-irtry packet
|
//Reset both counters when received a non-irtry packet
|
irtry_start_retry_cnt_comb = 6'h0;
|
irtry_start_retry_cnt_comb = 5'h0;
|
irtry_clear_error_cnt_comb = 6'h0;
|
irtry_clear_error_cnt_comb = 5'h0;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
//Save the temporary counts to be re-used in the next cycle and register the clear trigger
|
//Save the temporary counts to be re-used in the next cycle and register the clear trigger
|
| Line 765... |
Line 717... |
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk) begin `endif
|
always @(posedge clk) begin `endif
|
if(!res_n) begin
|
if(!res_n) begin
|
irtry_clear_trig <= 1'b0;
|
irtry_clear_trig <= 1'b0;
|
|
|
irtry_clear_error_cnt <= {6{1'b0}};
|
irtry_clear_error_cnt <= {5{1'b0}};
|
irtry_start_retry_cnt <= {6{1'b0}};
|
irtry_start_retry_cnt <= {5{1'b0}};
|
|
|
end else begin
|
end else begin
|
irtry_clear_trig <= irtry_clear_trig_comb;
|
irtry_clear_trig <= |flit_after_irtry_stage_is_clear_error_comb;
|
|
|
irtry_clear_error_cnt <= irtry_clear_error_cnt_comb;
|
irtry_clear_error_cnt <= irtry_clear_error_cnt_comb;
|
irtry_start_retry_cnt <= irtry_start_retry_cnt_comb;
|
irtry_start_retry_cnt <= irtry_start_retry_cnt_comb;
|
end
|
end
|
end
|
end
|
|
|
//Propagate data and apply the valid masks
|
//Propagate data and apply the valid masks
|
`ifdef ASYNC_RES
|
`ifdef ASYNC_RES
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk) begin `endif
|
always @(posedge clk) begin `endif
|
if(!res_n) begin
|
|
for(i_f = 0;i_f<(FPW);i_f=i_f+1) begin
|
|
flit_after_retry_stage[i_f] <= {128{1'b0}};
|
|
end
|
|
flit_after_retry_stage_is_hdr <= {FPW{1'b0}};
|
|
flit_after_retry_stage_is_tail <= {FPW{1'b0}};
|
|
flit_after_retry_stage_is_poisoned <= {FPW{1'b0}};
|
|
flit_after_retry_stage_is_flow <= {FPW{1'b0}};
|
|
flit_after_retry_stage_has_rtc <= {FPW{1'b0}};
|
|
flit_after_retry_stage_is_error <= {FPW{1'b0}};
|
|
flit_after_retry_stage_is_valid <= {FPW{1'b0}};
|
|
flit_after_retry_stage_is_start_retry <= 1'b0;
|
|
end else begin
|
|
|
|
for(i_f = 0;i_f<(FPW);i_f=i_f+1) begin
|
for(i_f = 0;i_f<(FPW);i_f=i_f+1) begin
|
flit_after_retry_stage[i_f] <= flit_after_lng_check[i_f];
|
`ifdef RESET_ALL
|
end
|
if(!res_n) flit_after_irtry_stage[i_f] <= {128{1'b0}};
|
flit_after_retry_stage_is_hdr <= flit_after_lng_check_is_hdr;
|
else
|
flit_after_retry_stage_is_tail <= flit_after_lng_check_is_tail;
|
`endif
|
flit_after_retry_stage_is_poisoned <= flit_after_lng_check_is_poisoned &
|
flit_after_irtry_stage[i_f] <= crc_d_out_flit[i_f];
|
flit_after_retry_stage_is_valid_mask_msb &
|
|
flit_after_retry_stage_is_valid_mask_lsb;
|
|
flit_after_retry_stage_is_flow <= flit_after_lng_check_is_flow;
|
|
flit_after_retry_stage_has_rtc <= flit_after_lng_check_has_rtc;
|
|
flit_after_retry_stage_is_error <= flit_after_lng_check_is_error;
|
|
flit_after_retry_stage_is_valid <= flit_after_lng_check_is_valid &
|
|
flit_after_retry_stage_is_valid_mask_msb &
|
|
flit_after_retry_stage_is_valid_mask_lsb;
|
|
flit_after_retry_stage_is_start_retry <= flit_after_retry_stage_is_start_retry_comb;
|
|
end
|
end
|
|
|
|
if(!res_n) begin
|
|
`ifdef RESET_ALL
|
|
flit_after_irtry_stage_is_hdr <= {FPW{1'b0}};
|
|
flit_after_irtry_stage_is_tail <= {FPW{1'b0}};
|
|
flit_after_irtry_stage_is_poisoned <= {FPW{1'b0}};
|
|
flit_after_irtry_stage_has_rtc <= {FPW{1'b0}};
|
|
flit_after_irtry_stage_is_error <= {FPW{1'b0}};
|
|
flit_after_irtry_stage_is_valid <= {FPW{1'b0}};
|
|
`endif
|
|
flit_after_irtry_stage_is_start_retry <= {FPW{1'b0}};
|
|
flit_after_irtry_stage_is_clear_error <= {FPW{1'b0}};
|
|
end else begin
|
|
|
|
flit_after_irtry_stage_is_start_retry <= flit_after_irtry_stage_is_start_retry_comb;
|
|
flit_after_irtry_stage_is_clear_error <= flit_after_irtry_stage_is_clear_error_comb;
|
|
end
|
|
flit_after_irtry_stage_is_hdr <= crc_d_out_flit_is_hdr;
|
|
flit_after_irtry_stage_is_tail <= crc_d_out_flit_is_tail;
|
|
flit_after_irtry_stage_is_poisoned <= crc_d_out_flit_is_poisoned;
|
|
flit_after_irtry_stage_has_rtc <= crc_d_out_flit_has_rtc;
|
|
flit_after_irtry_stage_is_error <= crc_d_out_flit_is_error;
|
|
flit_after_irtry_stage_is_valid <= crc_d_out_flit_is_valid;
|
end
|
end
|
|
|
//-------------------------------------------Error abort mode
|
//-------------------------------------------Error abort mode
|
`ifdef ASYNC_RES
|
`ifdef ASYNC_RES
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk or negedge res_n) begin `else
|
| Line 832... |
Line 785... |
tx_error_abort_mode <= 1'b0;
|
tx_error_abort_mode <= 1'b0;
|
tx_error_abort_mode_cleared <= 1'b1;
|
tx_error_abort_mode_cleared <= 1'b1;
|
end
|
end
|
|
|
//Set error abort mode again if error detected
|
//Set error abort mode again if error detected
|
if(|flit_after_lng_check_is_error || flit_after_seq_check_is_error)begin
|
if(|crc_d_out_flit_is_error || flit_after_seq_check_is_error)begin
|
tx_error_abort_mode <= 1'b1;
|
tx_error_abort_mode <= 1'b1;
|
end
|
end
|
|
|
end
|
end
|
end
|
end
|
| Line 850... |
Line 803... |
|
|
next_seqnum_comb = 3'h0;
|
next_seqnum_comb = 3'h0;
|
flit_after_seq_check_is_error_comb = {FPW{1'b0}};
|
flit_after_seq_check_is_error_comb = {FPW{1'b0}};
|
|
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
if(flit_after_retry_stage_has_rtc[i_f]) begin
|
if(flit_after_irtry_stage_has_rtc[i_f]) begin
|
//All packets that have an RTC also have a valid seqnum
|
//All packets that have an RTC also have a valid seqnum
|
if(seq(flit_after_retry_stage[i_f]) == next_seqnum + next_seqnum_comb) begin
|
|
next_seqnum_comb = next_seqnum_comb + 3'h1;
|
next_seqnum_comb = next_seqnum_comb + 3'h1;
|
end else begin
|
if(seq(flit_after_irtry_stage[i_f]) != (next_seqnum + next_seqnum_comb)) begin
|
flit_after_seq_check_is_error_comb[i_f] = 1'b1;
|
flit_after_seq_check_is_error_comb[i_f] = 1'b1;
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
`ifdef ASYNC_RES
|
`ifdef ASYNC_RES
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk) begin `endif
|
always @(posedge clk) begin `endif
|
|
|
|
for(i_f = 0;i_f<(FPW);i_f=i_f+1) begin
|
|
`ifdef RESET_ALL
|
|
if(!res_n) flit_after_seq_check[i_f] <= {128{1'b0}};
|
|
else
|
|
`endif
|
|
flit_after_seq_check[i_f] <= flit_after_irtry_stage[i_f];
|
|
end
|
|
|
if(!res_n) begin
|
if(!res_n) begin
|
|
|
//We expect the first packet to have the seqnum 1
|
next_seqnum <= 3'h0;
|
next_seqnum <= 3'h1;
|
|
|
|
|
`ifdef RESET_ALL
|
flit_after_seq_check_is_hdr <= {FPW{1'b0}};
|
flit_after_seq_check_is_hdr <= {FPW{1'b0}};
|
flit_after_seq_check_is_tail <= {FPW{1'b0}};
|
flit_after_seq_check_is_tail <= {FPW{1'b0}};
|
flit_after_seq_check_is_valid <= {FPW{1'b0}};
|
flit_after_seq_check_is_valid <= {FPW{1'b0}};
|
flit_after_seq_check_is_poisoned <= {FPW{1'b0}};
|
flit_after_seq_check_is_poisoned <= {FPW{1'b0}};
|
flit_after_seq_check_is_flow <= {FPW{1'b0}};
|
|
flit_after_seq_check_has_rtc <= {FPW{1'b0}};
|
flit_after_seq_check_has_rtc <= {FPW{1'b0}};
|
flit_after_seq_check_is_error <= {FPW{1'b0}};
|
|
flit_after_seq_check_is_start_retry <= {FPW{1'b0}};
|
flit_after_seq_check_is_start_retry <= {FPW{1'b0}};
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
flit_after_seq_check_is_clear_error <= {FPW{1'b0}};
|
flit_after_seq_check[i_f] <= {128{1'b0}};
|
`endif
|
end
|
flit_after_seq_check_is_error <= {FPW{1'b0}};
|
|
|
end else begin
|
end else begin
|
|
|
//Set the expected sequence number to the first one after error abort mode was cleared
|
//Set the expected sequence number to the first one after error abort mode was cleared
|
//otherwise apply the last seqnum + combinatioanl offset
|
//otherwise apply the last seqnum + combinatioanl offset
|
if(irtry_clear_trig_comb) begin
|
if(|flit_after_irtry_stage_is_clear_error_comb) begin
|
next_seqnum <= first_seq_after_error + next_seqnum_comb;
|
next_seqnum <= first_seq_after_error + next_seqnum_comb;
|
end else begin
|
end else begin
|
next_seqnum <= next_seqnum + next_seqnum_comb;
|
next_seqnum <= next_seqnum + next_seqnum_comb;
|
end
|
end
|
|
|
//propage data to next stage and include any error bits that were detected during sequence number check
|
//propage data to next stage and include any error bits that were detected during sequence number check
|
flit_after_seq_check_is_hdr <= flit_after_retry_stage_is_hdr;
|
flit_after_seq_check_is_error <= flit_after_irtry_stage_is_error |
|
flit_after_seq_check_is_tail <= flit_after_retry_stage_is_tail;
|
|
flit_after_seq_check_is_valid <= flit_after_retry_stage_is_valid;
|
|
flit_after_seq_check_is_poisoned <= flit_after_retry_stage_is_poisoned;
|
|
flit_after_seq_check_is_flow <= flit_after_retry_stage_is_flow;
|
|
flit_after_seq_check_has_rtc <= flit_after_retry_stage_has_rtc;
|
|
flit_after_seq_check_is_error <= flit_after_retry_stage_is_error |
|
|
flit_after_seq_check_is_error_comb;
|
flit_after_seq_check_is_error_comb;
|
flit_after_seq_check_is_start_retry <= flit_after_retry_stage_is_start_retry;
|
|
|
end
|
|
flit_after_seq_check_is_hdr <= flit_after_irtry_stage_is_hdr;
|
|
flit_after_seq_check_is_tail <= flit_after_irtry_stage_is_tail;
|
|
flit_after_seq_check_is_valid <= flit_after_irtry_stage_is_valid;
|
|
flit_after_seq_check_is_poisoned <= flit_after_irtry_stage_is_poisoned;
|
|
flit_after_seq_check_has_rtc <= flit_after_irtry_stage_has_rtc;
|
|
flit_after_seq_check_is_start_retry <= flit_after_irtry_stage_is_start_retry;
|
|
flit_after_seq_check_is_clear_error <= flit_after_irtry_stage_is_clear_error;
|
|
end
|
|
|
|
//==================================================================================
|
|
//---------------------------------Valid Mask - Remove valid bits for invalid FLITs
|
|
//==================================================================================
|
|
always@(*) begin
|
|
flit_after_mask_stage_is_valid_mask_lsb = {FPW{1'b0}};
|
|
flit_after_mask_stage_is_valid_mask_msb = {FPW{1'b0}};
|
|
for(i_f = FPW-1; i_f >=0; i_f = i_f - 1) begin
|
|
if(flit_after_seq_check_is_clear_error[i_f]) begin
|
|
flit_after_mask_stage_is_valid_mask_msb = {{FPW-1{1'b1}},1'b0} << i_f;
|
|
end
|
|
if(flit_after_seq_check_is_error[i_f]) begin
|
|
flit_after_mask_stage_is_valid_mask_lsb = {FPW{1'b1}} >> (FPW-i_f);
|
|
end
|
|
end
|
|
|
|
end
|
|
|
|
`ifdef ASYNC_RES
|
|
always @(posedge clk or negedge res_n) begin `else
|
|
always @(posedge clk) begin `endif
|
|
|
|
for(i_f = 0;i_f<(FPW);i_f=i_f+1) begin
|
|
flit_after_mask_stage[i_f] <= flit_after_seq_check[i_f];
|
|
end
|
|
|
|
if(!res_n) begin
|
|
|
|
`ifdef RESET_ALL
|
|
flit_after_mask_stage_is_hdr <= {FPW{1'b0}};
|
|
flit_after_mask_stage_is_tail <= {FPW{1'b0}};
|
|
flit_after_mask_stage_is_poisoned <= {FPW{1'b0}};
|
|
flit_after_mask_stage_has_rtc <= {FPW{1'b0}};
|
|
flit_after_mask_stage_is_error <= {FPW{1'b0}};
|
|
flit_after_mask_stage_is_start_retry <= 1'b0;
|
|
`endif
|
|
flit_after_mask_stage_is_valid <= {FPW{1'b0}};
|
|
error <= 1'b0;
|
|
end else begin
|
|
|
|
if(|flit_after_seq_check_is_clear_error)
|
|
error <= 1'b0;
|
|
|
|
if(|flit_after_seq_check_is_error)
|
|
error <= 1'b1;
|
|
|
|
casex({error,|flit_after_seq_check_is_clear_error,|flit_after_seq_check_is_error})
|
|
3'b000: begin
|
|
flit_after_mask_stage_is_valid <= flit_after_seq_check_is_valid;
|
|
end
|
|
3'b001: begin
|
|
flit_after_mask_stage_is_valid <= flit_after_seq_check_is_valid & flit_after_mask_stage_is_valid_mask_lsb;
|
|
end
|
|
3'bx10: begin
|
|
flit_after_mask_stage_is_valid <= flit_after_seq_check_is_valid & flit_after_mask_stage_is_valid_mask_msb;
|
|
end
|
|
3'bx11: begin
|
|
flit_after_mask_stage_is_valid <= flit_after_seq_check_is_valid & flit_after_mask_stage_is_valid_mask_msb & flit_after_mask_stage_is_valid_mask_lsb;
|
|
end
|
|
default: begin
|
|
flit_after_mask_stage_is_valid <= {FPW{1'b0}};
|
|
end
|
|
endcase
|
|
|
|
//propage data to next stage and include any error bits that were detected
|
|
|
|
end
|
|
flit_after_mask_stage_is_hdr <= flit_after_seq_check_is_hdr;
|
|
flit_after_mask_stage_is_tail <= flit_after_seq_check_is_tail;
|
|
flit_after_mask_stage_is_poisoned <= flit_after_seq_check_is_poisoned;
|
|
flit_after_mask_stage_has_rtc <= flit_after_seq_check_has_rtc;
|
|
flit_after_mask_stage_is_error <= flit_after_seq_check_is_error & flit_after_seq_check_is_tail;
|
|
flit_after_mask_stage_is_start_retry <= flit_after_seq_check_is_start_retry;
|
|
end
|
|
|
|
//==================================================================================
|
|
//---------------------------------Tokens/Pointers/Sequence numbers
|
|
//==================================================================================
|
|
//Count Tokens that were returned
|
|
always @(*) begin
|
|
rtc_sum_comb = {MAX_RTC_RET_LOG{1'b0}};
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
flit_after_seq_check[i_f] <= flit_after_retry_stage[i_f];
|
if(flit_after_mask_stage_has_rtc[i_f] && flit_after_mask_stage_is_valid[i_f])begin
|
|
rtc_sum_comb = rtc_sum_comb + rtc(flit_after_mask_stage[i_f]);
|
|
end
|
|
end
|
|
end
|
|
|
|
//Extract FRP/RRP + last seq (which is necessary to check packets after error_abort_mode is cleared)
|
|
`ifdef ASYNC_RES
|
|
always @(posedge clk or negedge res_n) begin `else
|
|
always @(posedge clk) begin `endif
|
|
if(!res_n) begin
|
|
|
|
tx_hmc_frp <= {8{1'b0}};
|
|
tx_rrp <= {8{1'b0}};
|
|
tx_returned_tokens <= {MAX_RTC_RET_LOG{1'b0}};
|
|
first_seq_after_error <= 3'h0;
|
|
tx_link_retry <= 1'b0;
|
|
|
|
end else begin
|
|
//Return tokens
|
|
tx_returned_tokens <= rtc_sum_comb;
|
|
|
|
//Process FLITs and extract frp/seq/rrp if applicable
|
|
for(i_f=0;i_f<(FPW);i_f=i_f+1) begin
|
|
|
|
if((flit_after_mask_stage_is_tail[i_f] && flit_after_mask_stage_is_valid[i_f]) || flit_after_mask_stage_is_start_retry[i_f]) begin
|
|
tx_rrp <= rrp(flit_after_mask_stage[i_f]);
|
|
end
|
|
|
|
if(flit_after_mask_stage_has_rtc[i_f] && flit_after_mask_stage_is_valid[i_f])begin
|
|
tx_hmc_frp <= frp(flit_after_mask_stage[i_f]);
|
|
first_seq_after_error <= seq(flit_after_mask_stage[i_f]);
|
|
end
|
|
end
|
|
|
|
//-------------------------------------------TX retry
|
|
tx_link_retry <= 1'b0;
|
|
|
|
if(|flit_after_mask_stage_is_start_retry)begin
|
|
tx_link_retry <= 1'b1;
|
end
|
end
|
|
|
end
|
end
|
end
|
end
|
|
|
//==================================================================================
|
//==================================================================================
|
//---------------------------------Retrieve the lengths to invalide FLITs
|
//---------------------------------Retrieve the lengths to invalidate FLITs
|
//==================================================================================
|
//==================================================================================
|
always @(*) begin
|
always @(*) begin
|
//Retrieve the length from the header and assign it to the tail. This information will be used in the
|
//Retrieve the length from the header and assign it to the tail. This information will be used in the
|
//invalidation stage to mask out FLITs that belong to the faulty packet
|
//invalidation stage to mask out FLITs that belong to the faulty packet
|
|
|
lng_comb = lng_temp;
|
lng_comb = lng_temp;
|
|
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
|
|
if(flit_after_retry_stage_is_hdr[i_f]) begin
|
if(flit_after_seq_check_is_hdr[i_f]) begin
|
if( lng(flit_after_retry_stage[i_f]) < 2 ||
|
if(flit_after_seq_check_is_error[i_f]) begin
|
lng(flit_after_retry_stage[i_f]) > 9
|
lng_comb = 4'h1;
|
) begin
|
|
lng_comb = 1;
|
|
end else begin
|
end else begin
|
lng_comb = lng(flit_after_retry_stage[i_f]);
|
lng_comb = lng(flit_after_seq_check[i_f]);
|
end
|
end
|
end
|
end
|
|
|
if(flit_after_retry_stage_is_tail[i_f]) begin
|
if(flit_after_seq_check_is_tail[i_f]) begin
|
lng_per_tail_comb[i_f] = lng_comb;
|
lng_per_tail_comb[i_f] = lng_comb;
|
end else begin
|
end else begin
|
lng_per_tail_comb[i_f] = {4{1'b0}};
|
lng_per_tail_comb[i_f] = 4'h0;
|
end
|
end
|
|
|
end
|
end
|
end
|
end
|
|
|
| Line 946... |
Line 1025... |
always @(posedge clk) begin `endif
|
always @(posedge clk) begin `endif
|
if(!res_n) begin
|
if(!res_n) begin
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
lng_per_tail[i_f] <= 0;
|
lng_per_tail[i_f] <= 0;
|
end
|
end
|
lng_temp <= {4{1'b0}};
|
lng_temp <= 4'h0;
|
end else begin
|
end else begin
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
lng_per_tail[i_f] <= lng_per_tail_comb[i_f];
|
lng_per_tail[i_f] <= lng_per_tail_comb[i_f];
|
end
|
end
|
lng_temp <= lng_comb;
|
lng_temp <= lng_comb;
|
| Line 962... |
Line 1041... |
//==================================================================================
|
//==================================================================================
|
//Constant propagation for some parts of the invalidation stage
|
//Constant propagation for some parts of the invalidation stage
|
`ifdef ASYNC_RES
|
`ifdef ASYNC_RES
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk) begin `endif
|
always @(posedge clk) begin `endif
|
|
|
|
`ifdef RESET_ALL
|
if(!res_n) begin
|
if(!res_n) begin
|
|
flit_in_invalidation_data[0] <= {DWIDTH{1'b0}};
|
|
|
for(i_c=0; i_c<(CYCLES_TO_COMPLETE_FULL_PACKET); i_c=i_c+1) begin
|
for(i_c=0; i_c<(CYCLES_TO_COMPLETE_FULL_PACKET-1); i_c=i_c+1) begin
|
flit_in_invalidation_data[i_c] <= {DWIDTH{1'b0}};
|
flit_in_invalidation_data[i_c+1] <= {DWIDTH{1'b0}};
|
flit_in_invalidation_is_hdr[i_c] <= {FPW{1'b0}};
|
|
flit_in_invalidation_is_tail[i_c] <= {FPW{1'b0}};
|
|
flit_in_invalidation_is_flow[i_c] <= {FPW{1'b0}};
|
|
flit_in_invalidation_has_rtc[i_c] <= {FPW{1'b0}};
|
|
flit_in_invalidation_is_start_retry[i_c] <= {FPW{1'b0}};
|
|
end
|
end
|
end else begin
|
end else
|
flit_in_invalidation_data[0] <= flit_after_seq_check_word;
|
`endif
|
flit_in_invalidation_is_hdr[0] <= flit_after_seq_check_is_hdr;
|
begin
|
flit_in_invalidation_is_tail[0] <= flit_after_seq_check_is_tail;
|
flit_in_invalidation_data[0] <= flit_after_mask_stage_word;
|
flit_in_invalidation_is_flow[0] <= flit_after_seq_check_is_flow;
|
|
flit_in_invalidation_has_rtc[0] <= flit_after_seq_check_has_rtc;
|
|
flit_in_invalidation_is_start_retry[0] <= flit_after_seq_check_is_start_retry;
|
|
|
|
for(i_c=0; i_c<(CYCLES_TO_COMPLETE_FULL_PACKET-1); i_c=i_c+1) begin
|
for(i_c=0; i_c<(CYCLES_TO_COMPLETE_FULL_PACKET-1); i_c=i_c+1) begin
|
flit_in_invalidation_data[i_c+1] <= flit_in_invalidation_data[i_c];
|
flit_in_invalidation_data[i_c+1] <= flit_in_invalidation_data[i_c];
|
|
end
|
|
end
|
|
|
|
flit_in_invalidation_is_hdr[0] <= flit_after_mask_stage_is_hdr;
|
|
flit_in_invalidation_is_tail[0] <= flit_after_mask_stage_is_tail;
|
|
|
|
for(i_c=0; i_c<(CYCLES_TO_COMPLETE_FULL_PACKET-1); i_c=i_c+1) begin
|
flit_in_invalidation_is_hdr[i_c+1] <= flit_in_invalidation_is_hdr[i_c];
|
flit_in_invalidation_is_hdr[i_c+1] <= flit_in_invalidation_is_hdr[i_c];
|
flit_in_invalidation_is_tail[i_c+1] <= flit_in_invalidation_is_tail[i_c];
|
flit_in_invalidation_is_tail[i_c+1] <= flit_in_invalidation_is_tail[i_c];
|
flit_in_invalidation_is_flow[i_c+1] <= flit_in_invalidation_is_flow[i_c];
|
|
flit_in_invalidation_has_rtc[i_c+1] <= flit_in_invalidation_has_rtc[i_c];
|
|
flit_in_invalidation_is_start_retry[i_c+1] <= flit_in_invalidation_is_start_retry[i_c];
|
|
end
|
|
end
|
end
|
end
|
end
|
|
|
//Mark all poisoned FLITs
|
//Mark all poisoned FLITs
|
always @(*) begin
|
always @(*) begin
|
flit_in_invalidation0_is_poisoned_comb = {FPW{1'b0}};
|
flit_in_invalidation0_is_poisoned_comb = {FPW{1'b0}};
|
for(i_f = FPW-1; i_f>=0; i_f = i_f-1) begin
|
for(i_f = FPW-1; i_f>=0; i_f = i_f-1) begin
|
if(flit_after_seq_check_is_poisoned[i_f])begin
|
if(flit_after_mask_stage_is_poisoned[i_f])begin
|
flit_in_invalidation0_is_poisoned_comb =flit_in_invalidation0_is_poisoned_comb |
|
flit_in_invalidation0_is_poisoned_comb =flit_in_invalidation0_is_poisoned_comb |
|
(({FPW{1'b1}} >> (FPW-i_f-1)) & ~({FPW{1'b1}} >> lng_per_tail[i_f]+(FPW-i_f-1)));
|
(({FPW{1'b1}} >> (FPW-i_f-1)) & ~({FPW{1'b1}} >> lng_per_tail[i_f]+(FPW-i_f-1)));
|
end
|
end
|
end
|
end
|
end
|
end
|
| Line 1007... |
Line 1084... |
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk) begin `endif
|
always @(posedge clk) begin `endif
|
if(!res_n) begin
|
if(!res_n) begin
|
|
|
for(i_c = 0; i_c < (CYCLES_TO_COMPLETE_FULL_PACKET); i_c = i_c + 1) begin
|
for(i_c = 0; i_c < (CYCLES_TO_COMPLETE_FULL_PACKET); i_c = i_c + 1) begin
|
flit_in_invalidation_is_poisoned[i_c] <= 0;
|
flit_in_invalidation_is_poisoned[i_c] <= {FPW{1'b0}};
|
end
|
end
|
|
|
end else begin
|
end else begin
|
flit_in_invalidation_is_poisoned[0] <= flit_in_invalidation0_is_poisoned_comb;
|
flit_in_invalidation_is_poisoned[0] <= flit_in_invalidation0_is_poisoned_comb;
|
|
|
| Line 1019... |
Line 1096... |
flit_in_invalidation_is_poisoned[i_c+1] <= flit_in_invalidation_is_poisoned[i_c];
|
flit_in_invalidation_is_poisoned[i_c+1] <= flit_in_invalidation_is_poisoned[i_c];
|
end
|
end
|
|
|
//If there is a poisoned packet mark all FLITs as such
|
//If there is a poisoned packet mark all FLITs as such
|
for(i_f = FPW-1; i_f>=0; i_f = i_f-1) begin
|
for(i_f = FPW-1; i_f>=0; i_f = i_f-1) begin
|
if(flit_after_seq_check_is_poisoned[i_f]) begin
|
if(flit_after_mask_stage_is_poisoned[i_f]) begin
|
|
|
// flit_in_invalidation_is_poisoned[0] <= ({FPW{1'b1}} >> (FPW-i_f-1)) & ~({FPW{1'b1}} >> lng_per_tail[i_f]+(FPW-i_f-1));
|
|
|
|
for(i_c = 0; i_c < (CYCLES_TO_COMPLETE_FULL_PACKET-1); i_c = i_c + 1) begin
|
for(i_c = 0; i_c < (CYCLES_TO_COMPLETE_FULL_PACKET-1); i_c = i_c + 1) begin
|
if(lng_per_tail[i_f] > ((i_c)*FPW)+i_f+1) begin
|
if(lng_per_tail[i_f] > ((i_c)*FPW)+i_f+1) begin
|
flit_in_invalidation_is_poisoned[i_c+1] <= flit_in_invalidation_is_poisoned[i_c] | ~({FPW{1'b1}} >> lng_per_tail[i_f]-(i_c*FPW)-i_f-1);
|
flit_in_invalidation_is_poisoned[i_c+1] <= flit_in_invalidation_is_poisoned[i_c] | ~({FPW{1'b1}} >> lng_per_tail[i_f]-(i_c*FPW)-i_f-1);
|
end
|
end
|
| Line 1042... |
Line 1117... |
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk) begin `endif
|
always @(posedge clk) begin `endif
|
if(!res_n) begin
|
if(!res_n) begin
|
|
|
for(i_c = 0; i_c < (CYCLES_TO_COMPLETE_FULL_PACKET); i_c = i_c + 1) begin
|
for(i_c = 0; i_c < (CYCLES_TO_COMPLETE_FULL_PACKET); i_c = i_c + 1) begin
|
flit_in_invalidation_is_valid[i_c] <= 0;
|
flit_in_invalidation_is_valid[i_c] <= {FPW{1'b0}};
|
end
|
end
|
error_detected <= 0;
|
flit_in_invalidation_mask_error <= {FPW{1'b0}};
|
flit_in_invalidation_mask_error <= {FPW{1'b1}};
|
|
|
|
end else begin
|
end else begin
|
|
|
//Reset the masks for invalidation stages
|
//Reset the masks for invalidation stages
|
flit_in_invalidation_mask_error <= {FPW{1'b1}};
|
flit_in_invalidation_mask_error <= {FPW{1'b1}};
|
|
|
if(irtry_clear_trig) begin
|
|
error_detected <= 0;
|
|
end
|
|
|
|
//Propate invalidation stages but apply error and poisoned masks to the second stage
|
//Propate invalidation stages but apply error and poisoned masks to the second stage
|
for(i_c = 1; i_c < (CYCLES_TO_COMPLETE_FULL_PACKET-1); i_c = i_c + 1) begin
|
for(i_c = 1; i_c < (CYCLES_TO_COMPLETE_FULL_PACKET-1); i_c = i_c + 1) begin
|
flit_in_invalidation_is_valid[i_c+1] <= flit_in_invalidation_is_valid[i_c];
|
flit_in_invalidation_is_valid[i_c+1] <= flit_in_invalidation_is_valid[i_c];
|
end
|
end
|
flit_in_invalidation_is_valid[1] <= flit_in_invalidation_is_valid[0] & flit_in_invalidation_mask_error;
|
flit_in_invalidation_is_valid[1] <= flit_in_invalidation_is_valid[0] & flit_in_invalidation_mask_error;
|
|
|
if(error_detected) begin
|
|
//There is no valid FLIT when an error was detected
|
|
flit_in_invalidation_is_valid[0] <= {FPW{1'b0}};
|
|
end else begin
|
|
//First apply valids from previous stage
|
//First apply valids from previous stage
|
flit_in_invalidation_is_valid[0] <= flit_after_seq_check_is_valid;
|
flit_in_invalidation_is_valid[0] <= flit_after_mask_stage_is_valid;
|
|
|
//At least one FLIT contained an error in its tail. Leave all FLITs before the error untouched
|
//At least one FLIT contained an error in its tail. Leave all FLITs before the error untouched
|
for(i_f = FPW-1; i_f>=0; i_f = i_f-1) begin
|
for(i_f = FPW-1; i_f>=0; i_f = i_f-1) begin
|
if(flit_after_seq_check_is_error[i_f] && flit_after_seq_check_is_tail[i_f]) begin
|
if(flit_after_mask_stage_is_error[i_f]) begin
|
error_detected <= 1'b1;
|
|
flit_in_invalidation_mask_error <= {FPW{1'b1}} >> (FPW-i_f-1+lng_per_tail[i_f]);
|
flit_in_invalidation_mask_error <= {FPW{1'b1}} >> (FPW-i_f-1+lng_per_tail[i_f]);
|
end
|
end
|
end
|
|
|
|
//Now use the length of the packet to invalidate FLITs that may reside in the next stages already
|
//Now use the length of the packet to invalidate FLITs that may reside in the next stages already
|
for(i_f = FPW-1; i_f>=0; i_f = i_f-1) begin
|
if(flit_after_mask_stage_is_error[i_f] && &flit_in_invalidation_mask_error) begin
|
if(flit_after_seq_check_is_error[i_f] && flit_after_seq_check_is_tail[i_f]) begin
|
|
for(i_c = 0; i_c < (CYCLES_TO_COMPLETE_FULL_PACKET-1); i_c = i_c + 1) begin
|
for(i_c = 0; i_c < (CYCLES_TO_COMPLETE_FULL_PACKET-1); i_c = i_c + 1) begin
|
if(lng_per_tail[i_f] > ((i_c)*FPW)+i_f+1) begin
|
if(lng_per_tail[i_f] > ((i_c)*FPW)+i_f+1) begin
|
flit_in_invalidation_is_valid[i_c+1] <= flit_in_invalidation_is_valid[i_c] &
|
flit_in_invalidation_is_valid[i_c+1] <= flit_in_invalidation_is_valid[i_c] &
|
({FPW{1'b1}} >> lng_per_tail[i_f]-(i_c*FPW)-i_f-1);
|
({FPW{1'b1}} >> lng_per_tail[i_f]-(i_c*FPW)-i_f-1);
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
|
end
|
|
end
|
|
|
|
//====================================================================
|
|
//---------------------------------FRP/RRP/RTC
|
|
//====================================================================
|
|
//Count Tokens that were returned
|
|
always @(*) begin
|
|
rtc_sum_comb = {8{1'b0}};
|
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
|
if(checked_flit_has_rtc[i_f])begin
|
|
rtc_sum_comb = rtc_sum_comb + rtc(checked_flit[i_f]);
|
|
end
|
|
end
|
|
end
|
|
|
|
//Extract FRP/RRP + last seq (which is necessary to check packets after error_abort_mode is cleared)
|
|
`ifdef ASYNC_RES
|
|
always @(posedge clk or negedge res_n) begin `else
|
|
always @(posedge clk) begin `endif
|
|
if(!res_n) begin
|
|
|
|
tx_hmc_frp <= {8{1'b0}};
|
|
tx_rrp <= {8{1'b0}};
|
|
tx_returned_tokens <= {8{1'b0}};
|
|
first_seq_after_error <= 3'h1;
|
|
|
|
tx_link_retry <= 1'b0;
|
|
|
|
end else begin
|
|
//Return tokens
|
|
tx_returned_tokens <= rtc_sum_comb;
|
|
|
|
//Process FLITs and extract frp/seq/rrp if applicable
|
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
|
|
|
if(checked_flit_is_tail[i_f] || checked_flit_is_start_retry[i_f]) begin
|
|
tx_rrp <= rrp(checked_flit[i_f]);
|
|
|
|
if(checked_flit_has_rtc[i_f])begin
|
|
tx_hmc_frp <= frp(checked_flit[i_f]);
|
|
first_seq_after_error <= seq(checked_flit[i_f]) + 3'h1;
|
|
end
|
|
end
|
|
end
|
|
|
|
//-------------------------------------------TX retry
|
|
tx_link_retry <= 1'b0;
|
|
|
|
if(|checked_flit_is_start_retry)begin
|
|
tx_link_retry <= 1'b1;
|
|
end
|
|
|
|
end
|
end
|
end
|
end
|
|
|
//==================================================================================
|
//==================================================================================
|
//---------------------------------Fill the input buffer with all response packets
|
//---------------------------------Fill the input buffer with all response packets
|
//==================================================================================
|
//==================================================================================
|
`ifdef ASYNC_RES
|
`ifdef ASYNC_RES
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk) begin `endif
|
always @(posedge clk) begin `endif
|
if(!res_n) begin
|
|
|
|
input_buffer_shift_in <= 1'b0;
|
|
input_buffer_valid <= {FPW{1'b0}};
|
|
input_buffer_is_hdr <= {FPW{1'b0}};
|
|
input_buffer_is_tail <= {FPW{1'b0}};
|
|
input_buffer_is_error_rsp <= {FPW{1'b0}};
|
|
|
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
input_buffer_d_in_flit[i_f] <= {128{1'b0}};
|
`ifdef RESET_ALL
|
end
|
if(!res_n) input_buffer_d_in_flit[i_f] <= {128{1'b0}};
|
|
else
|
end else begin
|
`endif
|
|
|
input_buffer_shift_in <= 1'b0;
|
|
input_buffer_is_error_rsp <= {FPW{1'b0}};
|
|
|
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
|
input_buffer_d_in_flit[i_f] <= {128{1'b0}};
|
|
|
|
//Flow and poisoned packets are not forwarded
|
|
if(checked_flit_is_valid[i_f]) begin
|
|
if(!checked_flit_is_flow[i_f] && !checked_flit_is_poisoned[i_f])begin
|
|
input_buffer_d_in_flit[i_f] <= checked_flit[i_f];
|
input_buffer_d_in_flit[i_f] <= checked_flit[i_f];
|
end
|
end
|
if(checked_flit_is_hdr[i_f] && (cmd(checked_flit[i_f])==CMD_RSP_ERROR)) begin
|
|
input_buffer_is_error_rsp[i_f] <= 1'b1;
|
|
end
|
|
end
|
|
end
|
|
|
|
//Mask out any flow or poisoned packets
|
|
input_buffer_valid <= checked_flit_is_valid &
|
|
~checked_flit_is_flow &
|
|
~checked_flit_is_poisoned;
|
|
input_buffer_is_hdr <= checked_flit_is_hdr &
|
|
~checked_flit_is_flow &
|
|
~checked_flit_is_poisoned;
|
|
input_buffer_is_tail <= checked_flit_is_tail &
|
|
~checked_flit_is_flow &
|
|
~checked_flit_is_poisoned;
|
|
|
|
//If there is still a valid packet remaining after applying the mask
|
|
if(|(checked_flit_is_valid & ~checked_flit_is_flow & ~checked_flit_is_poisoned))begin
|
|
input_buffer_shift_in <= 1'b1;
|
|
end
|
|
|
|
end
|
|
end
|
|
|
|
always @(*) begin
|
|
tokens_poisoned = {LOG_FPW+1{1'b0}};
|
|
|
|
for(i_f=0; i_f<FPW; i_f=i_f+1) begin
|
for(i_f=0; i_f<FPW; i_f=i_f+1) begin
|
tokens_poisoned = tokens_poisoned + checked_flit_is_poisoned[i_f];
|
input_buffer_is_error_rsp[i_f] <= checked_flit_is_hdr[i_f] && cmd(checked_flit[i_f])==CMD_RSP_ERROR;
|
end
|
input_buffer_is_hdr[i_f] <= checked_flit_is_hdr[i_f] && !checked_flit_is_poisoned[i_f] && !is_rsp_flow(checked_flit[i_f]);
|
|
input_buffer_is_valid[i_f] <= checked_flit_is_valid[i_f] && !checked_flit_is_poisoned[i_f] && !(is_rsp_flow(checked_flit[i_f]) && checked_flit_is_hdr[i_f]);
|
|
input_buffer_is_tail[i_f] <= checked_flit_is_tail[i_f] && !checked_flit_is_poisoned[i_f] && !(is_rsp_flow(checked_flit[i_f]) && checked_flit_is_hdr[i_f]);
|
end
|
end
|
|
|
`ifdef ASYNC_RES
|
|
always @(posedge clk or negedge res_n) begin `else
|
|
always @(posedge clk) begin `endif
|
|
if(!res_n) begin
|
|
tx_hmc_poisoned_tokens_to_return <= {LOG_FPW+1{1'b0}};
|
|
end else begin
|
|
tx_hmc_poisoned_tokens_to_return <= tokens_poisoned;
|
|
end
|
|
end
|
end
|
|
assign input_buffer_shift_in = |input_buffer_is_valid;
|
|
|
//==================================================================================
|
//==================================================================================
|
//---------------------------------Count responses and poisoned packets
|
//---------------------------------Count responses and poisoned packets
|
//==================================================================================
|
//==================================================================================
|
always @(*) begin
|
always @(*) begin
|
| Line 1238... |
Line 1198... |
rf_cnt_rsp_comb = rf_cnt_rsp_comb + {{LOG_FPW{1'b0}},1'b1};
|
rf_cnt_rsp_comb = rf_cnt_rsp_comb + {{LOG_FPW{1'b0}},1'b1};
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
|
`ifdef XILINX
|
|
//Use the openhmc_counter48_wrapper_xilinx in building_blocks/counter to directly instantiate DSP48
|
|
openhmc_counter48_wrapper_xilinx #(
|
|
.INC_SIZE(LOG_FPW+1),
|
|
.PIPELINED(XIL_CNT_PIPELINED)
|
|
)cnt_poisoned (
|
|
.clk(clk),
|
|
.res_n(res_n),
|
|
.inc_value(rf_cnt_poisoned_comb),
|
|
.value(rf_cnt_poisoned)
|
|
);
|
|
|
|
openhmc_counter48_wrapper_xilinx #(
|
|
.INC_SIZE(LOG_FPW+1),
|
|
.PIPELINED(XIL_CNT_PIPELINED)
|
|
)cnt_rsp (
|
|
.clk(clk),
|
|
.res_n(res_n),
|
|
.inc_value(rf_cnt_rsp_comb),
|
|
.value(rf_cnt_rsp)
|
|
);
|
|
|
|
`else
|
|
reg [RF_COUNTER_SIZE-1:0] rf_cnt_poisoned_temp;
|
|
reg [RF_COUNTER_SIZE-1:0] rf_cnt_rsp_temp;
|
|
assign rf_cnt_poisoned = rf_cnt_poisoned_temp;
|
|
assign rf_cnt_rsp = rf_cnt_rsp_temp;
|
|
|
`ifdef ASYNC_RES
|
`ifdef ASYNC_RES
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk) begin `endif
|
always @(posedge clk) begin `endif
|
if(!res_n) begin
|
if(!res_n) begin
|
rf_cnt_poisoned <= {HMC_RF_RWIDTH{1'b0}};
|
rf_cnt_poisoned_temp <= {RF_COUNTER_SIZE{1'b0}};
|
rf_cnt_rsp <= {HMC_RF_RWIDTH{1'b0}};
|
rf_cnt_rsp_temp <= {RF_COUNTER_SIZE{1'b0}};
|
end else begin
|
end else begin
|
rf_cnt_poisoned <= rf_cnt_poisoned + {{HMC_RF_RWIDTH-LOG_FPW-1{1'b0}},rf_cnt_poisoned_comb};
|
rf_cnt_poisoned_temp <= rf_cnt_poisoned_temp + {{RF_COUNTER_SIZE-LOG_FPW-1{1'b0}},rf_cnt_poisoned_comb};
|
rf_cnt_rsp <= rf_cnt_rsp + {{HMC_RF_RWIDTH-LOG_FPW-1{1'b0}},rf_cnt_rsp_comb};
|
rf_cnt_rsp_temp <= rf_cnt_rsp_temp + {{RF_COUNTER_SIZE-LOG_FPW-1{1'b0}},rf_cnt_rsp_comb};
|
end
|
end
|
end
|
end
|
|
`endif
|
|
|
|
|
//==================================================================================
|
//==================================================================================
|
//---------------------------------Shift response packets into the output fifo, return a token for each processed FLIT
|
//---------------------------------Return the tokens
|
//==================================================================================
|
//==================================================================================
|
|
generate
|
|
if(OPEN_RSP_MODE==0) begin : return_tokens
|
|
|
|
reg [MAX_RTC_RET_LOG-1:0] rtc_returned_tokens;
|
|
reg [MAX_RTC_RET_LOG-1:0] rtc_poisoned_tokens_to_return;
|
|
reg [LOG_FPW:0] tokens_out_of_fifo_sum_comb;
|
|
reg [LOG_FPW:0] tokens_poisoned;
|
|
|
|
assign tx_hmc_tokens_to_return = rtc_returned_tokens;
|
|
assign tx_hmc_poisoned_tokens_to_return = rtc_poisoned_tokens_to_return;
|
|
|
|
//Poisoned tokens will be returned before they enter the input buffer
|
|
always @(*) begin
|
|
tokens_poisoned = {LOG_FPW+1{1'b0}};
|
|
|
|
for(i_f=0; i_f<FPW; i_f=i_f+1) begin
|
|
tokens_poisoned = tokens_poisoned + checked_flit_is_poisoned[i_f];
|
|
end
|
|
end
|
|
|
|
//All other tokens will be returned as they leave the input buffer
|
always @(*) begin
|
always @(*) begin
|
tokens_out_of_fifo_sum_comb = {LOG_FPW+1{1'b0}};
|
tokens_out_of_fifo_sum_comb = {LOG_FPW+1{1'b0}};
|
|
|
if(input_buffer_shift_out)begin
|
if(input_buffer_shift_out)begin
|
for(i_f=0; i_f<FPW; i_f=i_f+1) begin
|
for(i_f=0; i_f<FPW; i_f=i_f+1) begin
|
| Line 1269... |
Line 1280... |
|
|
`ifdef ASYNC_RES
|
`ifdef ASYNC_RES
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk) begin `endif
|
always @(posedge clk) begin `endif
|
if(!res_n) begin
|
if(!res_n) begin
|
tx_hmc_tokens_to_return <= {LOG_FPW+1{1'b0}};
|
rtc_returned_tokens <= {LOG_FPW+1{1'b0}};
|
|
rtc_poisoned_tokens_to_return <= {LOG_FPW+1{1'b0}};
|
end else begin
|
end else begin
|
tx_hmc_tokens_to_return <= tokens_out_of_fifo_sum_comb;
|
rtc_returned_tokens <= tokens_out_of_fifo_sum_comb;
|
|
rtc_poisoned_tokens_to_return <= tokens_poisoned;
|
end
|
end
|
end
|
end
|
|
|
|
end else begin
|
|
//no input buffer, and no tokens will be returned
|
|
assign tx_hmc_tokens_to_return = {LOG_FPW+1{1'b0}};
|
|
assign tx_hmc_poisoned_tokens_to_return = {LOG_FPW+1{1'b0}};
|
|
end
|
|
endgenerate
|
|
|
|
|
|
|
|
//==================================================================================
|
|
//---------------------------------Shift response packets into the output fifo
|
|
//==================================================================================
|
|
generate
|
|
if(OPEN_RSP_MODE==0) begin : assign_output_data
|
|
|
|
reg [DWIDTH-1:0] out_data;
|
|
reg out_shift_in;
|
|
reg [4*FPW-1:0] out_ctrl;
|
|
|
|
assign d_out_fifo_data = out_data;
|
|
assign d_out_fifo_shift_in = out_shift_in;
|
|
assign d_out_fifo_ctrl = out_ctrl;
|
|
|
`ifdef ASYNC_RES
|
`ifdef ASYNC_RES
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk) begin `endif
|
always @(posedge clk) begin `endif
|
if(!res_n) begin
|
if(!res_n) begin
|
//----FIFO
|
//----FIFO
|
d_out_fifo_shift_in <= 1'b0;
|
out_shift_in <= 1'b0;
|
d_out_fifo_ctrl <= {4*FPW{1'b0}};
|
out_ctrl <= {4*FPW{1'b0}};
|
d_out_fifo_data <= {DWIDTH{1'b0}};
|
out_data <= {DWIDTH{1'b0}};
|
|
|
end else begin
|
end else begin
|
d_out_fifo_shift_in <= 1'b0;
|
|
d_out_fifo_ctrl <= {4*FPW{1'b0}};
|
|
|
|
|
|
if(input_buffer_shift_out)begin
|
if(input_buffer_shift_out)begin
|
d_out_fifo_data <= input_buffer_d_out[DWIDTH-1:0];
|
out_shift_in <= 1'b1;
|
d_out_fifo_shift_in <= 1'b1;
|
out_ctrl <= input_buffer_d_out[DWIDTH+(4*FPW)-1:DWIDTH];
|
d_out_fifo_ctrl <= input_buffer_d_out[DWIDTH+(4*FPW)-1:DWIDTH];
|
out_data <= input_buffer_d_out[DWIDTH-1:0];
|
|
end else begin
|
|
out_shift_in <= 1'b0;
|
|
end
|
end
|
end
|
end
|
end
|
|
end else begin //Open Response Mode
|
|
|
|
assign d_out_fifo_data = input_buffer_d_in[DWIDTH-1:0];
|
|
assign d_out_fifo_shift_in = input_buffer_shift_in;
|
|
assign d_out_fifo_ctrl = input_buffer_d_in[DWIDTH+(4*FPW)-1:DWIDTH];
|
|
|
end
|
end
|
|
endgenerate
|
|
|
|
|
|
|
//=====================================================================================================
|
//=====================================================================================================
|
//-----------------------------------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------------------------------
|
//---------INSTANTIATIONS HERE-------------------------------------------------------------------------
|
//---------INSTANTIATIONS HERE-------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------------------------------
|
//=====================================================================================================
|
//=====================================================================================================
|
|
|
wire res_n_lanes;
|
wire lanes_can_lock;
|
assign res_n_lanes = ((rf_link_status == LINK_DOWN) || !rf_hmc_init_cont_set) ? 1'b0 : 1'b1;
|
assign lanes_can_lock = (rf_hmc_sleep || !run_rx) ? 1'b0 : 1'b1;
|
|
//
|
//Lane Init
|
//Lane Init
|
genvar i;
|
genvar i;
|
generate
|
generate
|
for(i=0;i<NUM_LANES;i=i+1)begin : lane_gen
|
for(i=0;i<NUM_LANES;i=i+1)begin : lane_gen
|
rx_lane_logic #(
|
rx_lane_logic #(
|
| Line 1319... |
Line 1360... |
.NUM_LANES(NUM_LANES),
|
.NUM_LANES(NUM_LANES),
|
.CTRL_LANE_POLARITY(CTRL_LANE_POLARITY),
|
.CTRL_LANE_POLARITY(CTRL_LANE_POLARITY),
|
.BITSLIP_SHIFT_RIGHT(BITSLIP_SHIFT_RIGHT)
|
.BITSLIP_SHIFT_RIGHT(BITSLIP_SHIFT_RIGHT)
|
) rx_lane_I (
|
) rx_lane_I (
|
.clk(clk),
|
.clk(clk),
|
.res_n(res_n_lanes),
|
.res_n(res_n),
|
.bit_slip(init_bit_slip[i]),
|
.can_lock(lanes_can_lock),
|
|
.bit_slip(phy_bit_slip[i]),
|
.descrambler_locked(init_descrambler_locked[i]),
|
.descrambler_locked(init_descrambler_locked[i]),
|
.descrambler_disable(rf_scrambler_disable),
|
.descrambler_disable(rf_scrambler_disable),
|
.lane_polarity(rf_lane_polarity[i]),
|
.lane_polarity(rf_lane_polarity[i]),
|
.scrambled_data_in(phy_scrambled_data_in[i*WIDTH_PER_LANE+WIDTH_PER_LANE-1:i*WIDTH_PER_LANE]),
|
.scrambled_data_in(phy_scrambled_data_in[i*WIDTH_PER_LANE+WIDTH_PER_LANE-1:i*WIDTH_PER_LANE]),
|
.descrambled_data_out(descrambled_data_per_lane[i])
|
.descrambled_data_out(descrambled_data_per_lane[i])
|
| Line 1341... |
Line 1383... |
rx_crc_compare
|
rx_crc_compare
|
(
|
(
|
.clk(clk),
|
.clk(clk),
|
.res_n(res_n),
|
.res_n(res_n),
|
//input
|
//input
|
.d_in_data(data2crc),
|
.d_in_data(d_in_dly),
|
.d_in_hdr(data2crc_hdr),
|
.d_in_hdr(data2crc_hdr),
|
.d_in_tail(data2crc_tail),
|
.d_in_tail(data2crc_tail),
|
.d_in_valid(data2crc_valid),
|
.d_in_valid(data2crc_valid),
|
|
// .d_in_error(data2crc_error),
|
.d_in_lng(data2crc_lng),
|
.d_in_lng(data2crc_lng),
|
//output
|
//output
|
.d_out_data(crc_d_out_data),
|
.d_out_data(crc_d_out_data),
|
.d_out_hdr(crc_d_out_flit_is_hdr),
|
.d_out_hdr(crc_d_out_flit_is_hdr),
|
.d_out_tail(crc_d_out_flit_is_tail),
|
.d_out_tail(crc_d_out_flit_is_tail),
|
| Line 1357... |
Line 1400... |
.d_out_poisoned(crc_d_out_flit_is_poisoned),
|
.d_out_poisoned(crc_d_out_flit_is_poisoned),
|
.d_out_rtc(crc_d_out_flit_has_rtc),
|
.d_out_rtc(crc_d_out_flit_has_rtc),
|
.d_out_flow(crc_d_out_flit_is_flow)
|
.d_out_flow(crc_d_out_flit_is_flow)
|
);
|
);
|
|
|
|
generate
|
|
if(OPEN_RSP_MODE==0) begin : use_input_buffer
|
//Buffer Fifo - Depth = Max Tokens
|
//Buffer Fifo - Depth = Max Tokens
|
openhmc_sync_fifo #(
|
openhmc_sync_fifo #(
|
.DATASIZE(DWIDTH+(4*FPW)), //+4*FPW for header/tail/valid/error response information -> AXI-4 TUSER signal
|
.DATASIZE(DWIDTH+(4*FPW)), //+4*FPW for header/tail/valid/error response information -> AXI-4 TUSER signal
|
.ADDRSIZE(LOG_MAX_RTC)
|
.ADDRSIZE(LOG_MAX_RX_TOKENS)
|
) input_buffer_I(
|
) input_buffer_I(
|
.clk(clk),
|
.clk(clk),
|
.res_n(res_n),
|
.res_n(res_n),
|
.d_in(input_buffer_d_in),
|
.d_in(input_buffer_d_in),
|
.shift_in(input_buffer_shift_in),
|
.shift_in(input_buffer_shift_in),
|
.d_out(input_buffer_d_out),
|
.d_out(input_buffer_d_out),
|
.shift_out(input_buffer_shift_out),
|
.shift_out(input_buffer_shift_out),
|
.next_stage_full(1'b1), // Dont touch!
|
|
.empty(input_buffer_empty)
|
.empty(input_buffer_empty)
|
);
|
);
|
|
end
|
|
endgenerate
|
|
|
endmodule
|
endmodule
|
`default_nettype wire
|
`default_nettype wire
|
|
|
No newline at end of file
|
No newline at end of file
|
