?rev1line? |
?rev2line? |
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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 1991-2007 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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|
(including device programming or simulation files), and any
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|
associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
|
|
Subscription Agreement, Altera MegaCore Function License
|
|
Agreement, or other applicable license agreement, including,
|
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without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors. Please refer to the
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|
applicable agreement for further details.
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*/
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(header "symbol" (version "1.1"))
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|
(symbol
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(rect 16 16 136 112)
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(text "clock_mux" (rect 5 0 58 12)(font "Arial" ))
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(text "inst" (rect 8 80 25 92)(font "Arial" ))
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(port
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(pt 0 32)
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(input)
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|
(text "clk" (rect 0 0 14 12)(font "Arial" ))
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|
(text "clk" (rect 21 27 35 39)(font "Arial" ))
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|
(line (pt 0 32)(pt 16 32)(line_width 1))
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|
)
|
|
(port
|
|
(pt 0 48)
|
|
(input)
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|
(text "cks[2..0]" (rect 0 0 43 12)(font "Arial" ))
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|
(text "cks[2..0]" (rect 21 43 64 55)(font "Arial" ))
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|
(line (pt 0 48)(pt 16 48)(line_width 3))
|
|
)
|
|
(port
|
|
(pt 120 32)
|
|
(output)
|
|
(text "wcks" (rect 0 0 24 12)(font "Arial" ))
|
|
(text "wcks" (rect 75 27 99 39)(font "Arial" ))
|
|
(line (pt 120 32)(pt 104 32)(line_width 1))
|
|
)
|
|
(drawing
|
|
(rectangle (rect 16 16 104 80)(line_width 1))
|
|
)
|
|
)
|
