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-- Created by Ruben H. Mileca - May-16-2010
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library ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.all;
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entity serializer IS
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port (
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-- Internal
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clk: in std_logic; -- External 24 MHz oscillator
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-- FT245BM
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txe: in std_logic; -- From FT245BM TXE# pin
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rxf: in std_logic; -- From FT245BM RXF pin
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pwr: in std_logic; -- From FT245BM PWREN# pin
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rst: in std_logic; -- From FT245BM RSTOUT# pin
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wrk: in std_logic; -- From tap_sm working signal
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wr: out std_logic := '1'; -- To FT245BM WR pin
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rd: out std_logic := '1'; -- To FT245BM RD# pin
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siwu: out std_logic := '1'; -- To FT245BM SI/WU pin
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db: inout std_logic_vector(7 downto 0); -- From/To FT245BM data bus
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-- JTAG
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tdo: in std_logic; -- TDO Jtag pin
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tck: out std_logic := '0'; -- TCK Jtag pin
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tms: out std_logic := '0'; -- TMS Jtag pin
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tdi: out std_logic := '0'; -- TDI Jtag pin
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trst: out std_logic := '1'; -- TRST Jtag pin
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-- Clock and SM setting
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new_state: out std_logic_vector(3 downto 0); -- tap_sm new state
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cks: out std_logic_vector(2 downto 0) -- Clock divider
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);
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end serializer;
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architecture rtl of serializer is
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signal count: integer range 0 to 8 := 0;
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signal state: integer range 0 to 15 := 0;
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signal rclk: integer range 0 to 1 := 0;
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signal sclk: integer range 0 to 1 := 0;
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signal instr: integer range 0 to 1 := 0; -- 0=Instruction, 1=Data, 2=Shift out, 3/4 shift in
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signal ssm: integer range 0 to 15 := 0; -- Shift and data state machine
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signal dir: std_logic := '1'; -- '0' = MSB, '1' = LSB
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signal rtms: std_logic := '0'; -- TMS state at last shift bit
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signal shift: std_logic_vector(7 downto 0);
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signal rbyte: std_logic_vector(7 downto 0);
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begin
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changestate: process(clk, rclk, rxf, txe, pwr, rst)
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begin
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if (rising_edge(clk)) then
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if rclk = 1 then
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rclk <= 0;
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else
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rclk <= 1;
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end if;
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-- st <= std_logic_vector(to_unsigned(state, st'length));
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if wrk = '0' then
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case ssm is
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when 0 =>
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tck <= '0';
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tms <= '0';
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tdi <= '0';
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if rxf = '0' then -- Start byte read from FT245BM
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rd <= '0'; -- Send RD# to FT245BM
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ssm <= 1; -- Change to next state
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end if;
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when 1 =>
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rbyte <= db; -- Read byte from FT245BM
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db <= "ZZZZZZZZ";
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rd <= '1'; -- Select next byte from FT245BM
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ssm <= 2; -- Change state;
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when 2 =>
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case instr is
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when 0 => -- Is an instruction byte
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case rbyte(3 downto 0) is
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when "0000" => -- rbyte(7 downto 4) have the new clock divisor
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cks <= rbyte(7 downto 5); -- Set clock divisor
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when "0001" => -- rbyte(7 downto 4) have then new state
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new_state <= rbyte(7 downto 4);
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ssm <= 3; -- Reset state machine
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when "0010" => -- Get current TAP state
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rbyte(3 downto 0) <= std_logic_vector(to_unsigned(state, rbyte(3 downto 0)'length));
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rbyte(4) <= dir;
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ssm <= 5;
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when "0011" => -- Software reset TAP
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count <= to_integer(unsigned(rbyte(7 downto 4)));
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ssm <= 9;
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tms <= '1';
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when "0100" => -- Hardware reset TAP
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count <= to_integer(unsigned(rbyte(7 downto 4)) - 1);
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ssm <= 8;
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when "0101" => -- Set MSB/LSB shift direction
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dir <= rbyte(4); -- Set shift direction
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sclk <= 0;
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ssm <= 0; -- Reset state machine
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when "0110" => -- Latch the next byte as shift data
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if state = 0 or state = 4 or state = 11 then
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count <= to_integer(unsigned(rbyte(7 downto 5)));
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rtms <= rbyte(4); -- TMS state at last shifted bit
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instr <= 1; -- Next is data to send
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sclk <= 0;
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ssm <= 0; -- Reset state machine
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end if;
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when others =>
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ssm <= 0; -- Error, reset state machine
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end case;
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when 1 => -- There is a count bits to shift in/out
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-- st <= std_logic_vector(to_unsigned(count, st'length));
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if sclk = 0 then
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tck <= '0';
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if dir = '0' then
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tdi <= rbyte(7);
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rbyte(7 downto 1) <= rbyte(6 downto 0);
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else
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tdi <= rbyte(0);
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rbyte(6 downto 0) <= rbyte(7 downto 1);
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end if;
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sclk <= 1;
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if count = 0 then
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tms <= rtms;
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end if;
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else
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tck <= '1';
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-- Read TDO
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if dir = '1' then
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shift(6 downto 0) <= shift(7 downto 1);
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shift(7) <= tdo;
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else
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shift(7 downto 1) <= shift(6 downto 0);
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shift(0) <= tdo;
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end if;
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if count > 0 then
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count <= count - 1;
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else
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ssm <= 5;
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instr <= 0;
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end if;
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sclk <= 0;
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end if;
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when others =>
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end case;
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-- Delay for SM state start to work
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when 3 =>
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ssm <= 4;
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when 4 =>
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ssm <= 0;
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-- Write rbyte to data bus
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when 5 =>
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tck <= '0';
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tms <= '0';
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tdi <= '0';
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if txe = '0' then
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ssm <= 6;
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db <= shift;
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end if;
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when 6 =>
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wr <= '0';
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ssm <= 7;
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when 7 =>
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wr <= '1';
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ssm <= 0;
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db <= "ZZZZZZZZ";
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if rtms = '1' then
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if state = 4 or state = 11 then
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state <= state + 1;
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end if;
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else
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if state = 0 then
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state <= state + 1;
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end if;
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end if;
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when 8 =>
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if count = 0 then
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trst <= '1';
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ssm <= 0;
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else
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trst <= '0';
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count <= count - 1;
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end if;
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when 9 =>
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if sclk = 0 then
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tck <= '1';
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else
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tck <= '0';
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if count > 0 then
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count <= count - 1;
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else
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tms <= '0';
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ssm <= 0;
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end if;
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end if;
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when others =>
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end case;
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end if;
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end if;
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end process changestate;
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end rtl;
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