| Line 29... |
Line 29... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 192 $
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// $Rev: 200 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2013-12-17 21:15:28 +0100 (Tue, 17 Dec 2013) $
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// $LastChangedDate: 2015-01-21 23:01:31 +0100 (Wed, 21 Jan 2015) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`include "timescale.v"
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`include "timescale.v"
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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| Line 99... |
Line 99... |
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// Peripheral templates
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// Peripheral templates
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wire [15:0] per_dout_temp_8b;
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wire [15:0] per_dout_temp_8b;
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wire [15:0] per_dout_temp_16b;
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wire [15:0] per_dout_temp_16b;
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// Simple full duplex UART
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wire [15:0] per_dout_uart;
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wire irq_uart_rx;
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wire irq_uart_tx;
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wire uart_txd;
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reg uart_rxd;
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// Timer A
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// Timer A
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wire irq_ta0;
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wire irq_ta0;
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wire irq_ta1;
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wire irq_ta1;
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wire [15:0] per_dout_timerA;
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wire [15:0] per_dout_timerA;
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reg inclk;
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reg inclk;
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| Line 196... |
Line 189... |
wire [31:0] inst_number;
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wire [31:0] inst_number;
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wire [15:0] inst_pc;
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wire [15:0] inst_pc;
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wire [8*32-1:0] inst_short;
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wire [8*32-1:0] inst_short;
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// Testbench variables
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// Testbench variables
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integer tb_idx;
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integer error;
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integer error;
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reg stimulus_done;
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reg stimulus_done;
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//
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//
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| Line 211... |
Line 205... |
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// Debug interface tasks
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// Debug interface tasks
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`include "dbg_uart_tasks.v"
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`include "dbg_uart_tasks.v"
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`include "dbg_i2c_tasks.v"
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`include "dbg_i2c_tasks.v"
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// Simple uart tasks
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//`include "uart_tasks.v"
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// Verilog stimulus
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// Verilog stimulus
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`include "stimulus.v"
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`include "stimulus.v"
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//
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//
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// Initialize ROM
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// Initialize Memory
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//------------------------------
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//------------------------------
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initial
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initial
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begin
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begin
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// Initialize data memory
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for (tb_idx=0; tb_idx < `DMEM_SIZE/2; tb_idx=tb_idx+1)
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dmem_0.mem[tb_idx] = 16'h0000;
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// Initialize program memory
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#10 $readmemh("./pmem.mem", pmem_0.mem);
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#10 $readmemh("./pmem.mem", pmem_0.mem);
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end
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end
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//
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//
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// Generate Clock & Reset
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// Generate Clock & Reset
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//------------------------------
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//------------------------------
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initial
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initial
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begin
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begin
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| Line 303... |
Line 300... |
ta_cci0b = 1'b0;
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ta_cci0b = 1'b0;
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ta_cci1a = 1'b0;
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ta_cci1a = 1'b0;
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ta_cci1b = 1'b0;
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ta_cci1b = 1'b0;
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ta_cci2a = 1'b0;
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ta_cci2a = 1'b0;
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ta_cci2b = 1'b0;
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ta_cci2b = 1'b0;
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uart_rxd = 1'b1;
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scan_enable = 1'b0;
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scan_enable = 1'b0;
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scan_mode = 1'b0;
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scan_mode = 1'b0;
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end
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end
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| Line 496... |
Line 492... |
.ta_cci2a (ta_cci2a), // Timer A compare 2 input A
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.ta_cci2a (ta_cci2a), // Timer A compare 2 input A
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.ta_cci2b (ta_cci2b), // Timer A compare 2 input B
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.ta_cci2b (ta_cci2b), // Timer A compare 2 input B
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.taclk (taclk) // TACLK external timer clock (SLOW)
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.taclk (taclk) // TACLK external timer clock (SLOW)
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);
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);
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//
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// Simple full duplex UART (8N1 protocol)
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//----------------------------------------
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`ifdef READY_FOR_PRIMETIME
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omsp_uart #(.BASE_ADDR(15'h0080)) uart_0 (
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// OUTPUTs
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.irq_uart_rx (irq_uart_rx), // UART receive interrupt
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.irq_uart_tx (irq_uart_tx), // UART transmit interrupt
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.per_dout (per_dout_uart), // Peripheral data output
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.uart_txd (uart_txd), // UART Data Transmit (TXD)
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// INPUTs
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.mclk (mclk), // Main system clock
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.per_addr (per_addr), // Peripheral address
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.per_din (per_din), // Peripheral data input
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.per_en (per_en), // Peripheral enable (high active)
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.per_we (per_we), // Peripheral write enable (high active)
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.puc_rst (puc_rst), // Main system reset
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.smclk_en (smclk_en), // SMCLK enable (from CPU)
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.uart_rxd (uart_rxd) // UART Data Receive (RXD)
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);
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`else
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assign irq_uart_rx = 1'b0;
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assign irq_uart_tx = 1'b0;
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assign per_dout_uart = 16'h0000;
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assign uart_txd = 1'b0;
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`endif
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//
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//
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// Peripheral templates
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// Peripheral templates
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//----------------------------------
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//----------------------------------
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|
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| Line 567... |
Line 535... |
// Combine peripheral data bus
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// Combine peripheral data bus
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//----------------------------------
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//----------------------------------
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|
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assign per_dout = per_dout_dio |
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assign per_dout = per_dout_dio |
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per_dout_timerA |
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per_dout_timerA |
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per_dout_uart |
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per_dout_temp_8b |
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per_dout_temp_8b |
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per_dout_temp_16b;
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per_dout_temp_16b;
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|
|
|
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//
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//
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| Line 582... |
Line 549... |
1'b0, // Vector 12 (0xFFF8)
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1'b0, // Vector 12 (0xFFF8)
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1'b0, // Vector 11 (0xFFF6)
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1'b0, // Vector 11 (0xFFF6)
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1'b0, // Vector 10 (0xFFF4) - Watchdog -
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1'b0, // Vector 10 (0xFFF4) - Watchdog -
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irq_ta0, // Vector 9 (0xFFF2)
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irq_ta0, // Vector 9 (0xFFF2)
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irq_ta1, // Vector 8 (0xFFF0)
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irq_ta1, // Vector 8 (0xFFF0)
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irq_uart_rx, // Vector 7 (0xFFEE)
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1'b0, // Vector 7 (0xFFEE)
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irq_uart_tx, // Vector 6 (0xFFEC)
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1'b0, // Vector 6 (0xFFEC)
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1'b0, // Vector 5 (0xFFEA)
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1'b0, // Vector 5 (0xFFEA)
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1'b0, // Vector 4 (0xFFE8)
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1'b0, // Vector 4 (0xFFE8)
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irq_port2, // Vector 3 (0xFFE6)
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irq_port2, // Vector 3 (0xFFE6)
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irq_port1, // Vector 2 (0xFFE4)
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irq_port1, // Vector 2 (0xFFE4)
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1'b0, // Vector 1 (0xFFE2)
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1'b0, // Vector 1 (0xFFE2)
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