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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [omsp_clock_module.v] - Diff between revs 134 and 180

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Rev 134 Rev 180
Line 34... Line 34...
//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 134 $
// $Rev: 180 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $
// $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`ifdef OMSP_NO_INCLUDE
`else
`else
`include "openMSP430_defines.v"
`include "openMSP430_defines.v"
`endif
`endif
Line 192... Line 192...
//--------------
//--------------
reg  [7:0] bcsctl1;
reg  [7:0] bcsctl1;
wire       bcsctl1_wr  = BCSCTL1[0] ? reg_hi_wr[BCSCTL1] : reg_lo_wr[BCSCTL1];
wire       bcsctl1_wr  = BCSCTL1[0] ? reg_hi_wr[BCSCTL1] : reg_lo_wr[BCSCTL1];
wire [7:0] bcsctl1_nxt = BCSCTL1[0] ? per_din[15:8]      : per_din[7:0];
wire [7:0] bcsctl1_nxt = BCSCTL1[0] ? per_din[15:8]      : per_din[7:0];
 
 
`ifdef ASIC
`ifdef ASIC_CLOCKING
  `ifdef ACLK_DIVIDER
  `ifdef ACLK_DIVIDER
wire [7:0] divax_mask = 8'h30;
wire [7:0] divax_mask = 8'h30;
  `else
  `else
wire [7:0] divax_mask = 8'h00;
wire [7:0] divax_mask = 8'h00;
  `endif
  `endif
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`ifdef MCLK_DIVIDER
`ifdef MCLK_DIVIDER
wire [7:0] divmx_mask = 8'h30;
wire [7:0] divmx_mask = 8'h30;
`else
`else
wire [7:0] divmx_mask = 8'h00;
wire [7:0] divmx_mask = 8'h00;
`endif
`endif
`ifdef ASIC
`ifdef ASIC_CLOCKING
  `ifdef SMCLK_MUX
  `ifdef SMCLK_MUX
wire [7:0] sels_mask  = 8'h08;
wire [7:0] sels_mask  = 8'h08;
  `else
  `else
wire [7:0] sels_mask  = 8'h00;
wire [7:0] sels_mask  = 8'h00;
  `endif
  `endif
Line 261... Line 261...
 
 
//=============================================================================
//=============================================================================
// 5)  DCO_CLK / LFXT_CLK INTERFACES (WAKEUP, ENABLE, ...)
// 5)  DCO_CLK / LFXT_CLK INTERFACES (WAKEUP, ENABLE, ...)
//=============================================================================
//=============================================================================
 
 
`ifdef ASIC
`ifdef ASIC_CLOCKING
   wire cpuoff_and_mclk_enable;
   wire cpuoff_and_mclk_enable;
   omsp_and_gate and_cpuoff_mclk_en (.y(cpuoff_and_mclk_enable), .a(cpuoff), .b(mclk_enable));
   omsp_and_gate and_cpuoff_mclk_en (.y(cpuoff_and_mclk_enable), .a(cpuoff), .b(mclk_enable));
`endif
`endif
 
 
//-----------------------------------------------------------
//-----------------------------------------------------------
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// ASIC MODE
// ASIC MODE
//------------------------------------------------
//------------------------------------------------
// Note: unlike the original MSP430 specification,
// Note: unlike the original MSP430 specification,
//       we allow to switch off the LFXT even
//       we allow to switch off the LFXT even
//       if it is selected by MCLK or SMCLK.
//       if it is selected by MCLK or SMCLK.
`ifdef ASIC
`ifdef ASIC_CLOCKING
 
 
`ifdef OSCOFF_EN
`ifdef OSCOFF_EN
 
 
   // The LFXT is synchronously disabled if:
   // The LFXT is synchronously disabled if:
   //      - the cpu pin is disabled (in that case, wait for mclk_enable==0)
   //      - the cpu pin is disabled (in that case, wait for mclk_enable==0)
Line 524... Line 524...
`endif
`endif
 
 
// Synchronize CPU_EN signal to the SMCLK domain
// Synchronize CPU_EN signal to the SMCLK domain
//----------------------------------------------
//----------------------------------------------
// Note: the synchronizer is only required if there is a SMCLK_MUX
// Note: the synchronizer is only required if there is a SMCLK_MUX
`ifdef ASIC
`ifdef ASIC_CLOCKING
  `ifdef SMCLK_MUX
  `ifdef SMCLK_MUX
     wire cpu_en_sm_s;
     wire cpu_en_sm_s;
     omsp_sync_cell sync_cell_cpu_sm_en (
     omsp_sync_cell sync_cell_cpu_sm_en (
        .data_out  (cpu_en_sm_s),
        .data_out  (cpu_en_sm_s),
        .data_in   (cpu_en),
        .data_in   (cpu_en),
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// 6.3) ACLK GENERATION
// 6.3) ACLK GENERATION
//-----------------------------------------------------------
//-----------------------------------------------------------
 
 
// ASIC MODE
// ASIC MODE
//----------------------------
//----------------------------
`ifdef ASIC
`ifdef ASIC_CLOCKING
 
 
  `ifdef ACLK_DIVIDER
  `ifdef ACLK_DIVIDER
    `ifdef LFXT_DOMAIN
    `ifdef LFXT_DOMAIN
 
 
   wire nodiv_aclk = lfxt_clk;
   wire nodiv_aclk = lfxt_clk;
Line 756... Line 756...
`endif
`endif
 
 
 
 
// ASIC MODE
// ASIC MODE
//----------------------------
//----------------------------
`ifdef ASIC
`ifdef ASIC_CLOCKING
  `ifdef SMCLK_MUX
  `ifdef SMCLK_MUX
 
 
    // Synchronizers
    // Synchronizers
    //------------------------------------------------------
    //------------------------------------------------------
    // When the SMCLK MUX is enabled, the reset and DIVSx
    // When the SMCLK MUX is enabled, the reset and DIVSx
Line 914... Line 914...
 
 
 
 
// Serial Debug Interface Clock gate
// Serial Debug Interface Clock gate
//------------------------------------------------
//------------------------------------------------
`ifdef DBG_EN
`ifdef DBG_EN
  `ifdef ASIC
  `ifdef ASIC_CLOCKING
  omsp_clock_gate clock_gate_dbg_clk (
  omsp_clock_gate clock_gate_dbg_clk (
      .gclk        (dbg_clk),
      .gclk        (dbg_clk),
      .clk         (mclk),
      .clk         (mclk),
      .enable      (dbg_en_s),
      .enable      (dbg_en_s),
      .scan_enable (scan_enable)
      .scan_enable (scan_enable)

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