| Line 29... |
Line 29... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 103 $
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// $Rev: 106 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
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// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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| Line 48... |
Line 48... |
brk_dout, // Hardware break/watch-point register data input
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brk_dout, // Hardware break/watch-point register data input
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// INPUTs
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// INPUTs
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brk_reg_rd, // Hardware break/watch-point register read select
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brk_reg_rd, // Hardware break/watch-point register read select
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brk_reg_wr, // Hardware break/watch-point register write select
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brk_reg_wr, // Hardware break/watch-point register write select
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dbg_clk, // Debug unit clock
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dbg_din, // Debug register data input
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dbg_din, // Debug register data input
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dbg_rst, // Debug unit reset
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eu_mab, // Execution-Unit Memory address bus
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eu_mab, // Execution-Unit Memory address bus
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eu_mb_en, // Execution-Unit Memory bus enable
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eu_mb_en, // Execution-Unit Memory bus enable
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eu_mb_wr, // Execution-Unit Memory bus write transfer
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eu_mb_wr, // Execution-Unit Memory bus write transfer
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eu_mdb_in, // Memory data bus input
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eu_mdb_in, // Memory data bus input
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eu_mdb_out, // Memory data bus output
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eu_mdb_out, // Memory data bus output
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exec_done, // Execution completed
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exec_done, // Execution completed
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fe_mb_en, // Frontend Memory bus enable
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fe_mb_en, // Frontend Memory bus enable
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mclk, // Main system clock
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pc // Program counter
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pc, // Program counter
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por // Power on reset
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);
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);
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// OUTPUTs
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// OUTPUTs
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//=========
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//=========
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output brk_halt; // Hardware breakpoint command
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output brk_halt; // Hardware breakpoint command
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| Line 71... |
Line 71... |
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// INPUTs
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// INPUTs
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//=========
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//=========
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input [3:0] brk_reg_rd; // Hardware break/watch-point register read select
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input [3:0] brk_reg_rd; // Hardware break/watch-point register read select
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input [3:0] brk_reg_wr; // Hardware break/watch-point register write select
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input [3:0] brk_reg_wr; // Hardware break/watch-point register write select
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input dbg_clk; // Debug unit clock
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input [15:0] dbg_din; // Debug register data input
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input [15:0] dbg_din; // Debug register data input
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input dbg_rst; // Debug unit reset
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input [15:0] eu_mab; // Execution-Unit Memory address bus
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input [15:0] eu_mab; // Execution-Unit Memory address bus
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input eu_mb_en; // Execution-Unit Memory bus enable
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input eu_mb_en; // Execution-Unit Memory bus enable
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input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer
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input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer
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input [15:0] eu_mdb_in; // Memory data bus input
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input [15:0] eu_mdb_in; // Memory data bus input
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input [15:0] eu_mdb_out; // Memory data bus output
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input [15:0] eu_mdb_out; // Memory data bus output
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input exec_done; // Execution completed
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input exec_done; // Execution completed
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input fe_mb_en; // Frontend Memory bus enable
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input fe_mb_en; // Frontend Memory bus enable
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input mclk; // Main system clock
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input [15:0] pc; // Program counter
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input [15:0] pc; // Program counter
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input por; // Power on reset
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//=============================================================================
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//=============================================================================
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// 1) WIRE & PARAMETER DECLARATION
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// 1) WIRE & PARAMETER DECLARATION
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//=============================================================================
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//=============================================================================
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| Line 131... |
Line 131... |
//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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reg [4:0] brk_ctl;
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reg [4:0] brk_ctl;
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wire brk_ctl_wr = brk_reg_wr[BRK_CTL];
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wire brk_ctl_wr = brk_reg_wr[BRK_CTL];
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always @ (posedge mclk or posedge por)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (por) brk_ctl <= 5'h00;
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if (dbg_rst) brk_ctl <= 5'h00;
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else if (brk_ctl_wr) brk_ctl <= {`HWBRK_RANGE & dbg_din[4], dbg_din[3:0]};
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else if (brk_ctl_wr) brk_ctl <= {`HWBRK_RANGE & dbg_din[4], dbg_din[3:0]};
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wire [7:0] brk_ctl_full = {3'b000, brk_ctl};
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wire [7:0] brk_ctl_full = {3'b000, brk_ctl};
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| Line 152... |
Line 152... |
range_rd_set & `HWBRK_RANGE,
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range_rd_set & `HWBRK_RANGE,
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addr1_wr_set, addr1_rd_set,
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addr1_wr_set, addr1_rd_set,
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addr0_wr_set, addr0_rd_set};
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addr0_wr_set, addr0_rd_set};
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wire [5:0] brk_stat_clr = ~dbg_din[5:0];
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wire [5:0] brk_stat_clr = ~dbg_din[5:0];
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always @ (posedge mclk or posedge por)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (por) brk_stat <= 6'h00;
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if (dbg_rst) brk_stat <= 6'h00;
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else if (brk_stat_wr) brk_stat <= ((brk_stat & brk_stat_clr) | brk_stat_set);
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else if (brk_stat_wr) brk_stat <= ((brk_stat & brk_stat_clr) | brk_stat_set);
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else brk_stat <= (brk_stat | brk_stat_set);
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else brk_stat <= (brk_stat | brk_stat_set);
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wire [7:0] brk_stat_full = {2'b00, brk_stat};
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wire [7:0] brk_stat_full = {2'b00, brk_stat};
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wire brk_pnd = |brk_stat;
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wire brk_pnd = |brk_stat;
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| Line 167... |
Line 167... |
//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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reg [15:0] brk_addr0;
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reg [15:0] brk_addr0;
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wire brk_addr0_wr = brk_reg_wr[BRK_ADDR0];
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wire brk_addr0_wr = brk_reg_wr[BRK_ADDR0];
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always @ (posedge mclk or posedge por)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (por) brk_addr0 <= 16'h0000;
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if (dbg_rst) brk_addr0 <= 16'h0000;
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else if (brk_addr0_wr) brk_addr0 <= dbg_din;
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else if (brk_addr0_wr) brk_addr0 <= dbg_din;
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// BRK_ADDR1/DATA0 Register
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// BRK_ADDR1/DATA0 Register
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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reg [15:0] brk_addr1;
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reg [15:0] brk_addr1;
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wire brk_addr1_wr = brk_reg_wr[BRK_ADDR1];
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wire brk_addr1_wr = brk_reg_wr[BRK_ADDR1];
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always @ (posedge mclk or posedge por)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (por) brk_addr1 <= 16'h0000;
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if (dbg_rst) brk_addr1 <= 16'h0000;
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else if (brk_addr1_wr) brk_addr1 <= dbg_din;
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else if (brk_addr1_wr) brk_addr1 <= dbg_din;
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//============================================================================
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//============================================================================
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// 3) DATA OUTPUT GENERATION
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// 3) DATA OUTPUT GENERATION
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| Line 213... |
Line 213... |
wire equ_d_addr1 = eu_mb_en & (eu_mab==brk_addr1) & ~brk_ctl[`BRK_RANGE];
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wire equ_d_addr1 = eu_mb_en & (eu_mab==brk_addr1) & ~brk_ctl[`BRK_RANGE];
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wire equ_d_range = eu_mb_en & ((eu_mab>=brk_addr0) & (eu_mab<=brk_addr1)) &
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wire equ_d_range = eu_mb_en & ((eu_mab>=brk_addr0) & (eu_mab<=brk_addr1)) &
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brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
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brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
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reg fe_mb_en_buf;
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reg fe_mb_en_buf;
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always @ (posedge mclk or posedge por)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (por) fe_mb_en_buf <= 1'b0;
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if (dbg_rst) fe_mb_en_buf <= 1'b0;
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else fe_mb_en_buf <= fe_mb_en;
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else fe_mb_en_buf <= fe_mb_en;
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wire equ_i_addr0 = fe_mb_en_buf & (pc==brk_addr0) & ~brk_ctl[`BRK_RANGE];
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wire equ_i_addr0 = fe_mb_en_buf & (pc==brk_addr0) & ~brk_ctl[`BRK_RANGE];
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wire equ_i_addr1 = fe_mb_en_buf & (pc==brk_addr1) & ~brk_ctl[`BRK_RANGE];
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wire equ_i_addr1 = fe_mb_en_buf & (pc==brk_addr1) & ~brk_ctl[`BRK_RANGE];
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wire equ_i_range = fe_mb_en_buf & ((pc>=brk_addr0) & (pc<=brk_addr1)) &
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wire equ_i_range = fe_mb_en_buf & ((pc>=brk_addr0) & (pc<=brk_addr1)) &
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| Line 242... |
Line 242... |
// Whenever an "ADD r9. &0x200" instruction is executed, &0x200 will be read
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// Whenever an "ADD r9. &0x200" instruction is executed, &0x200 will be read
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// before being written back. In that case, the read flag should not be set.
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// before being written back. In that case, the read flag should not be set.
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// In general, We should here make sure no write access occures during the
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// In general, We should here make sure no write access occures during the
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// same instruction cycle before setting the read flag.
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// same instruction cycle before setting the read flag.
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reg [2:0] d_rd_trig;
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reg [2:0] d_rd_trig;
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always @ (posedge mclk or posedge por)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (por) d_rd_trig <= 3'h0;
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if (dbg_rst) d_rd_trig <= 3'h0;
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else if (exec_done) d_rd_trig <= 3'h0;
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else if (exec_done) d_rd_trig <= 3'h0;
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else d_rd_trig <= {equ_d_range & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr,
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else d_rd_trig <= {equ_d_range & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr,
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equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr,
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equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr,
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equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr};
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equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr};
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