| Line 54... |
Line 54... |
mclk, // Main system clock
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mclk, // Main system clock
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per_addr, // Peripheral address
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per_addr, // Peripheral address
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per_din, // Peripheral data input
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per_din, // Peripheral data input
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per_en, // Peripheral enable (high active)
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per_en, // Peripheral enable (high active)
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per_we, // Peripheral write enable (high active)
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per_we, // Peripheral write enable (high active)
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puc_rst // Main system reset
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puc_rst, // Main system reset
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scan_enable // Scan enable (active during scan shifting)
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);
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);
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// OUTPUTs
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// OUTPUTs
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//=========
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//=========
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output [15:0] per_dout; // Peripheral data output
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output [15:0] per_dout; // Peripheral data output
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| Line 69... |
Line 70... |
input [13:0] per_addr; // Peripheral address
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input [13:0] per_addr; // Peripheral address
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input [15:0] per_din; // Peripheral data input
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input [15:0] per_din; // Peripheral data input
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input per_en; // Peripheral enable (high active)
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input per_en; // Peripheral enable (high active)
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input [1:0] per_we; // Peripheral write enable (high active)
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input [1:0] per_we; // Peripheral write enable (high active)
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input puc_rst; // Main system reset
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input puc_rst; // Main system reset
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input scan_enable; // Scan enable (active during scan shifting)
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//=============================================================================
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//=============================================================================
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// 1) PARAMETER/REGISTERS & WIRE DECLARATION
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// 1) PARAMETER/REGISTERS & WIRE DECLARATION
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//=============================================================================
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//=============================================================================
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| Line 92... |
Line 94... |
RESLO = 'hA,
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RESLO = 'hA,
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RESHI = 'hC,
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RESHI = 'hC,
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SUMEXT = 'hE;
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SUMEXT = 'hE;
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// Register one-hot decoder utilities
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// Register one-hot decoder utilities
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parameter DEC_SZ = 2**DEC_WD;
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parameter DEC_SZ = (1 << DEC_WD);
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parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
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parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
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// Register one-hot decoder
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// Register one-hot decoder
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parameter [DEC_SZ-1:0] OP1_MPY_D = (BASE_REG << OP1_MPY),
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parameter [DEC_SZ-1:0] OP1_MPY_D = (BASE_REG << OP1_MPY),
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OP1_MPYS_D = (BASE_REG << OP1_MPYS),
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OP1_MPYS_D = (BASE_REG << OP1_MPYS),
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| Line 154... |
Line 156... |
wire op1_wr = reg_wr[OP1_MPY] |
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wire op1_wr = reg_wr[OP1_MPY] |
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reg_wr[OP1_MPYS] |
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reg_wr[OP1_MPYS] |
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reg_wr[OP1_MAC] |
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reg_wr[OP1_MAC] |
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reg_wr[OP1_MACS];
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reg_wr[OP1_MACS];
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always @ (posedge mclk or posedge puc_rst)
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`ifdef CLOCK_GATING
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wire mclk_op1;
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omsp_clock_gate clock_gate_op1 (.gclk(mclk_op1),
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.clk (mclk), .enable(op1_wr), .scan_enable(scan_enable));
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`else
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wire mclk_op1 = mclk;
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`endif
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always @ (posedge mclk_op1 or posedge puc_rst)
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if (puc_rst) op1 <= 16'h0000;
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if (puc_rst) op1 <= 16'h0000;
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`ifdef CLOCK_GATING
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else op1 <= per_din;
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`else
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else if (op1_wr) op1 <= per_din;
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else if (op1_wr) op1 <= per_din;
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`endif
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wire [15:0] op1_rd = op1;
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wire [15:0] op1_rd = op1;
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// OP2 Register
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// OP2 Register
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//-----------------
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//-----------------
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reg [15:0] op2;
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reg [15:0] op2;
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wire op2_wr = reg_wr[OP2];
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wire op2_wr = reg_wr[OP2];
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always @ (posedge mclk or posedge puc_rst)
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`ifdef CLOCK_GATING
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wire mclk_op2;
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omsp_clock_gate clock_gate_op2 (.gclk(mclk_op2),
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.clk (mclk), .enable(op2_wr), .scan_enable(scan_enable));
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`else
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wire mclk_op2 = mclk;
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`endif
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always @ (posedge mclk_op2 or posedge puc_rst)
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if (puc_rst) op2 <= 16'h0000;
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if (puc_rst) op2 <= 16'h0000;
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`ifdef CLOCK_GATING
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else op2 <= per_din;
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`else
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else if (op2_wr) op2 <= per_din;
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else if (op2_wr) op2 <= per_din;
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`endif
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wire [15:0] op2_rd = op2;
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wire [15:0] op2_rd = op2;
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// RESLO Register
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// RESLO Register
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| Line 181... |
Line 207... |
reg [15:0] reslo;
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reg [15:0] reslo;
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wire [15:0] reslo_nxt;
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wire [15:0] reslo_nxt;
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wire reslo_wr = reg_wr[RESLO];
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wire reslo_wr = reg_wr[RESLO];
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always @ (posedge mclk or posedge puc_rst)
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`ifdef CLOCK_GATING
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wire reslo_en = reslo_wr | result_clr | result_wr;
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wire mclk_reslo;
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omsp_clock_gate clock_gate_reslo (.gclk(mclk_reslo),
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.clk (mclk), .enable(reslo_en), .scan_enable(scan_enable));
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`else
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wire mclk_reslo = mclk;
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`endif
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always @ (posedge mclk_reslo or posedge puc_rst)
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if (puc_rst) reslo <= 16'h0000;
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if (puc_rst) reslo <= 16'h0000;
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else if (reslo_wr) reslo <= per_din;
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else if (reslo_wr) reslo <= per_din;
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else if (result_clr) reslo <= 16'h0000;
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else if (result_clr) reslo <= 16'h0000;
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`ifdef CLOCK_GATING
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else reslo <= reslo_nxt;
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`else
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else if (result_wr) reslo <= reslo_nxt;
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else if (result_wr) reslo <= reslo_nxt;
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`endif
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wire [15:0] reslo_rd = early_read ? reslo_nxt : reslo;
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wire [15:0] reslo_rd = early_read ? reslo_nxt : reslo;
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// RESHI Register
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// RESHI Register
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| Line 197... |
Line 236... |
reg [15:0] reshi;
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reg [15:0] reshi;
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wire [15:0] reshi_nxt;
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wire [15:0] reshi_nxt;
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wire reshi_wr = reg_wr[RESHI];
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wire reshi_wr = reg_wr[RESHI];
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always @ (posedge mclk or posedge puc_rst)
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`ifdef CLOCK_GATING
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wire reshi_en = reshi_wr | result_clr | result_wr;
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wire mclk_reshi;
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omsp_clock_gate clock_gate_reshi (.gclk(mclk_reshi),
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.clk (mclk), .enable(reshi_en), .scan_enable(scan_enable));
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`else
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wire mclk_reshi = mclk;
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`endif
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always @ (posedge mclk_reshi or posedge puc_rst)
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if (puc_rst) reshi <= 16'h0000;
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if (puc_rst) reshi <= 16'h0000;
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else if (reshi_wr) reshi <= per_din;
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else if (reshi_wr) reshi <= per_din;
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else if (result_clr) reshi <= 16'h0000;
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else if (result_clr) reshi <= 16'h0000;
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`ifdef CLOCK_GATING
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else reshi <= reshi_nxt;
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`else
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else if (result_wr) reshi <= reshi_nxt;
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else if (result_wr) reshi <= reshi_nxt;
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`endif
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wire [15:0] reshi_rd = early_read ? reshi_nxt : reshi;
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wire [15:0] reshi_rd = early_read ? reshi_nxt : reshi;
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// SUMEXT Register
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// SUMEXT Register
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| Line 252... |
Line 304... |
// Multiplier configuration
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// Multiplier configuration
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//--------------------------
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//--------------------------
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// Detect signed mode
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// Detect signed mode
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reg sign_sel;
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reg sign_sel;
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always @ (posedge mclk or posedge puc_rst)
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always @ (posedge mclk_op1 or posedge puc_rst)
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if (puc_rst) sign_sel <= 1'b0;
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if (puc_rst) sign_sel <= 1'b0;
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`ifdef CLOCK_GATING
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else sign_sel <= reg_wr[OP1_MPYS] | reg_wr[OP1_MACS];
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`else
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else if (op1_wr) sign_sel <= reg_wr[OP1_MPYS] | reg_wr[OP1_MACS];
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else if (op1_wr) sign_sel <= reg_wr[OP1_MPYS] | reg_wr[OP1_MACS];
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`endif
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// Detect accumulate mode
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// Detect accumulate mode
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reg acc_sel;
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reg acc_sel;
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always @ (posedge mclk or posedge puc_rst)
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always @ (posedge mclk_op1 or posedge puc_rst)
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if (puc_rst) acc_sel <= 1'b0;
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if (puc_rst) acc_sel <= 1'b0;
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`ifdef CLOCK_GATING
|
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else acc_sel <= reg_wr[OP1_MAC] | reg_wr[OP1_MACS];
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`else
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else if (op1_wr) acc_sel <= reg_wr[OP1_MAC] | reg_wr[OP1_MACS];
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else if (op1_wr) acc_sel <= reg_wr[OP1_MAC] | reg_wr[OP1_MACS];
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`endif
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// Detect whenever the RESHI and RESLO registers should be cleared
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// Detect whenever the RESHI and RESLO registers should be cleared
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assign result_clr = op2_wr & ~acc_sel;
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assign result_clr = op2_wr & ~acc_sel;
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