| Line 29... |
Line 29... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 103 $
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// $Rev: 106 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
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// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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| Line 53... |
Line 53... |
mclk, // Main system clock
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mclk, // Main system clock
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nmi_acc, // Non-Maskable interrupt request accepted
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nmi_acc, // Non-Maskable interrupt request accepted
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per_addr, // Peripheral address
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per_addr, // Peripheral address
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per_din, // Peripheral data input
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per_din, // Peripheral data input
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per_en, // Peripheral enable (high active)
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per_en, // Peripheral enable (high active)
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per_wen, // Peripheral write enable (high active)
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per_we, // Peripheral write enable (high active)
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por, // Power-on reset
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por, // Power-on reset
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puc, // Main system reset
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puc, // Main system reset
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wdtifg_clr, // Clear Watchdog-timer interrupt flag
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wdtifg_clr, // Clear Watchdog-timer interrupt flag
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wdtifg_set, // Set Watchdog-timer interrupt flag
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wdtifg_set, // Set Watchdog-timer interrupt flag
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wdtpw_error, // Watchdog-timer password error
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wdtpw_error, // Watchdog-timer password error
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| Line 77... |
Line 77... |
input mclk; // Main system clock
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input mclk; // Main system clock
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input nmi_acc; // Non-Maskable interrupt request accepted
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input nmi_acc; // Non-Maskable interrupt request accepted
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input [7:0] per_addr; // Peripheral address
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input [7:0] per_addr; // Peripheral address
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input [15:0] per_din; // Peripheral data input
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input [15:0] per_din; // Peripheral data input
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input per_en; // Peripheral enable (high active)
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input per_en; // Peripheral enable (high active)
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input [1:0] per_wen; // Peripheral write enable (high active)
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input [1:0] per_we; // Peripheral write enable (high active)
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input por; // Power-on reset
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input por; // Power-on reset
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input puc; // Main system reset
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input puc; // Main system reset
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input wdtifg_clr; // Clear Watchdog-timer interrupt flag
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input wdtifg_clr; // Clear Watchdog-timer interrupt flag
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input wdtifg_set; // Set Watchdog-timer interrupt flag
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input wdtifg_set; // Set Watchdog-timer interrupt flag
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input wdtpw_error; // Watchdog-timer password error
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input wdtpw_error; // Watchdog-timer password error
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| Line 113... |
Line 113... |
(IFG1 /2): reg_dec = IFG1_D;
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(IFG1 /2): reg_dec = IFG1_D;
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default : reg_dec = {256{1'b0}};
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default : reg_dec = {256{1'b0}};
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endcase
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endcase
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// Read/Write probes
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// Read/Write probes
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wire reg_lo_write = per_wen[0] & per_en;
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wire reg_lo_write = per_we[0] & per_en;
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wire reg_hi_write = per_wen[1] & per_en;
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wire reg_hi_write = per_we[1] & per_en;
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wire reg_read = ~|per_wen & per_en;
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wire reg_read = ~|per_we & per_en;
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// Read/Write vectors
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// Read/Write vectors
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wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}};
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wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}};
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wire [255:0] reg_lo_wr = reg_dec & {256{reg_lo_write}};
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wire [255:0] reg_lo_wr = reg_dec & {256{reg_lo_write}};
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wire [255:0] reg_rd = reg_dec & {256{reg_read}};
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wire [255:0] reg_rd = reg_dec & {256{reg_read}};
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