OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [openMSP430.v] - Diff between revs 105 and 106

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 105 Rev 106
Line 29... Line 29... 
//
 
//
 
// *Author(s):
 
// *Author(s):
 
//              - Olivier Girard,    olgirard@gmail.com
 
//              - Olivier Girard,    olgirard@gmail.com
 
//
 
//
 
//----------------------------------------------------------------------------
 
//----------------------------------------------------------------------------
 
// $Rev: 105 $
 
// $Rev: 106 $
 
// $LastChangedBy: olivier.girard $
 
// $LastChangedBy: olivier.girard $
 
// $LastChangedDate: 2011-03-10 22:10:30 +0100 (Thu, 10 Mar 2011) $
 
// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
 
//----------------------------------------------------------------------------
 
//----------------------------------------------------------------------------
 
`ifdef OMSP_NO_INCLUDE
 
`ifdef OMSP_NO_INCLUDE
 
`else
 
`else
 
`include "openMSP430_defines.v"
 
`include "openMSP430_defines.v"
 
`endif
 
`endif
Line 52... Line 52... 
    dmem_wen,                      // Data Memory write enable (low active)
 
    dmem_wen,                      // Data Memory write enable (low active)
 
    irq_acc,                       // Interrupt request accepted (one-hot signal)
 
    irq_acc,                       // Interrupt request accepted (one-hot signal)
 
    mclk,                          // Main system clock
 
    mclk,                          // Main system clock
 
    per_addr,                      // Peripheral address
 
    per_addr,                      // Peripheral address
 
    per_din,                       // Peripheral data input
 
    per_din,                       // Peripheral data input
 
    per_wen,                       // Peripheral write enable (high active)
 
    per_we,                        // Peripheral write enable (high active)
 
    per_en,                        // Peripheral enable (high active)
 
    per_en,                        // Peripheral enable (high active)
 
    pmem_addr,                     // Program Memory address
 
    pmem_addr,                     // Program Memory address
 
    pmem_cen,                      // Program Memory chip enable (low active)
 
    pmem_cen,                      // Program Memory chip enable (low active)
 
    pmem_din,                      // Program Memory data input (optional)
 
    pmem_din,                      // Program Memory data input (optional)
 
    pmem_wen,                      // Program Memory write enable (low active) (optional)
 
    pmem_wen,                      // Program Memory write enable (low active) (optional)
 
    puc,                           // Main system reset
 
    puc,                           // Main system reset
 
    smclk_en,                      // SMCLK enable
 
    smclk_en,                      // SMCLK enable
 
 
 
 
 
// INPUTs
 
// INPUTs
 
    dbg_uart_rxd,                  // Debug interface: UART RXD
 
    cpu_en,                        // Enable CPU code execution (asynchronous)
 
 
 
    dbg_en,                        // Debug interface enable (asynchronous)
 
 
 
    dbg_uart_rxd,                  // Debug interface: UART RXD (asynchronous)
 
    dco_clk,                       // Fast oscillator (fast clock)
 
    dco_clk,                       // Fast oscillator (fast clock)
 
    dmem_dout,                     // Data Memory data output
 
    dmem_dout,                     // Data Memory data output
 
    irq,                           // Maskable interrupts
 
    irq,                           // Maskable interrupts
 
    lfxt_clk,                      // Low frequency oscillator (typ 32kHz)
 
    lfxt_clk,                      // Low frequency oscillator (typ 32kHz)
 
    nmi,                           // Non-maskable interrupt (asynchronous)
 
    nmi,                           // Non-maskable interrupt (asynchronous)
 
    per_dout,                      // Peripheral data output
 
    per_dout,                      // Peripheral data output
 
    pmem_dout,                     // Program Memory data output
 
    pmem_dout,                     // Program Memory data output
 
    reset_n                        // Reset Pin (low active)
 
    reset_n                        // Reset Pin (low active, asynchronous)
 
);
 
);
 
 
 
 
 
// OUTPUTs
 
// OUTPUTs
 
//=========
 
//=========
 
output               aclk_en;      // ACLK enable
 
output               aclk_en;      // ACLK enable
Line 86... Line 88... 
output         [1:0] dmem_wen;     // Data Memory write enable (low active)
 
output         [1:0] dmem_wen;     // Data Memory write enable (low active)
 
output        [13:0] irq_acc;      // Interrupt request accepted (one-hot signal)
 
output        [13:0] irq_acc;      // Interrupt request accepted (one-hot signal)
 
output               mclk;         // Main system clock
 
output               mclk;         // Main system clock
 
output         [7:0] per_addr;     // Peripheral address
 
output         [7:0] per_addr;     // Peripheral address
 
output        [15:0] per_din;      // Peripheral data input
 
output        [15:0] per_din;      // Peripheral data input
 
output         [1:0] per_wen;      // Peripheral write enable (high active)
 
output         [1:0] per_we;       // Peripheral write enable (high active)
 
output               per_en;       // Peripheral enable (high active)
 
output               per_en;       // Peripheral enable (high active)
 
output [`PMEM_MSB:0] pmem_addr;    // Program Memory address
 
output [`PMEM_MSB:0] pmem_addr;    // Program Memory address
 
output               pmem_cen;     // Program Memory chip enable (low active)
 
output               pmem_cen;     // Program Memory chip enable (low active)
 
output        [15:0] pmem_din;     // Program Memory data input (optional)
 
output        [15:0] pmem_din;     // Program Memory data input (optional)
 
output         [1:0] pmem_wen;     // Program Memory write enable (low active) (optional)
 
output         [1:0] pmem_wen;     // Program Memory write enable (low active) (optional)
Line 98... Line 100... 
output               smclk_en;     // SMCLK enable
 
output               smclk_en;     // SMCLK enable
 
 
 
 
 
 
 
 
 
// INPUTs
 
// INPUTs
 
//=========
 
//=========
 
input                dbg_uart_rxd; // Debug interface: UART RXD
 
input                cpu_en;       // Enable CPU code execution (asynchronous)
 
 
 
input                dbg_en;       // Debug interface enable (asynchronous)
 
 
 
input                dbg_uart_rxd; // Debug interface: UART RXD (asynchronous)
 
input                dco_clk;      // Fast oscillator (fast clock)
 
input                dco_clk;      // Fast oscillator (fast clock)
 
input         [15:0] dmem_dout;    // Data Memory data output
 
input         [15:0] dmem_dout;    // Data Memory data output
 
input         [13:0] irq;          // Maskable interrupts
 
input         [13:0] irq;          // Maskable interrupts
 
input                lfxt_clk;     // Low frequency oscillator (typ 32kHz)
 
input                lfxt_clk;     // Low frequency oscillator (typ 32kHz)
 
input                nmi;          // Non-maskable interrupt (asynchronous)
 
input                nmi;          // Non-maskable interrupt (asynchronous)
 
input         [15:0] per_dout;     // Peripheral data output
 
input         [15:0] per_dout;     // Peripheral data output
 
input         [15:0] pmem_dout;    // Program Memory data output
 
input         [15:0] pmem_dout;    // Program Memory data output
 
input                reset_n;      // Reset Pin (active low)
 
input                reset_n;      // Reset Pin (active low, asynchronous)
 
 
 
 
 
 
 
 
 
 
 
 
 
//=============================================================================
 
//=============================================================================
 
// 1)  INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
 
// 1)  INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
Line 142... Line 146... 
wire         [15:0] pc_nxt;
 
wire         [15:0] pc_nxt;
 
 
 
 
 
wire                dbg_halt_cmd;
 
wire                dbg_halt_cmd;
 
wire                dbg_mem_en;
 
wire                dbg_mem_en;
 
wire                dbg_reg_wr;
 
wire                dbg_reg_wr;
 
wire                dbg_reset;
 
wire                dbg_cpu_reset;
 
wire         [15:0] dbg_mem_addr;
 
wire         [15:0] dbg_mem_addr;
 
wire         [15:0] dbg_mem_dout;
 
wire         [15:0] dbg_mem_dout;
 
wire         [15:0] dbg_mem_din;
 
wire         [15:0] dbg_mem_din;
 
wire         [15:0] dbg_reg_din;
 
wire         [15:0] dbg_reg_din;
 
wire          [1:0] dbg_mem_wr;
 
wire          [1:0] dbg_mem_wr;
Line 164... Line 168... 
 
 
 
 
omsp_clock_module clock_module_0 (
 
omsp_clock_module clock_module_0 (
 
 
 
 
 
// OUTPUTs
 
// OUTPUTs
 
    .aclk_en      (aclk_en),       // ACLK enablex
 
    .aclk_en      (aclk_en),       // ACLK enablex
 
 
 
    .cpu_en_s     (cpu_en_s),      // Enable CPU code execution (synchronous)
 
 
 
    .dbg_clk      (dbg_clk),       // Debug unit clock
 
 
 
    .dbg_en_s     (dbg_en_s),      // Debug interface enable (synchronous)
 
 
 
    .dbg_rst      (dbg_rst),       // Debug unit reset
 
    .mclk         (mclk),          // Main system clock
 
    .mclk         (mclk),          // Main system clock
 
    .per_dout     (per_dout_clk),  // Peripheral data output
 
    .per_dout     (per_dout_clk),  // Peripheral data output
 
    .por          (por),           // Power-on reset
 
    .por          (por),           // Power-on reset
 
    .puc          (puc),           // Main system reset
 
    .puc          (puc),           // Main system reset
 
    .smclk_en     (smclk_en),      // SMCLK enable
 
    .smclk_en     (smclk_en),      // SMCLK enable
 
 
 
 
 
// INPUTs
 
// INPUTs
 
    .dbg_reset    (dbg_reset),     // Reset CPU from debug interface
 
    .cpu_en       (cpu_en),        // Enable CPU code execution (asynchronous)
 
 
 
    .dbg_cpu_reset(dbg_cpu_reset), // Reset CPU from debug interface
 
 
 
    .dbg_en       (dbg_en),        // Debug interface enable (asynchronous)
 
    .dco_clk      (dco_clk),       // Fast oscillator (fast clock)
 
    .dco_clk      (dco_clk),       // Fast oscillator (fast clock)
 
    .lfxt_clk     (lfxt_clk),      // Low frequency oscillator (typ 32kHz)
 
    .lfxt_clk     (lfxt_clk),      // Low frequency oscillator (typ 32kHz)
 
    .oscoff       (oscoff),        // Turns off LFXT1 clock input
 
    .oscoff       (oscoff),        // Turns off LFXT1 clock input
 
    .per_addr     (per_addr),      // Peripheral address
 
    .per_addr     (per_addr),      // Peripheral address
 
    .per_din      (per_din),       // Peripheral data input
 
    .per_din      (per_din),       // Peripheral data input
 
    .per_en       (per_en),        // Peripheral enable (high active)
 
    .per_en       (per_en),        // Peripheral enable (high active)
 
    .per_wen      (per_wen),       // Peripheral write enable (high active)
 
    .per_we       (per_we),        // Peripheral write enable (high active)
 
    .reset_n      (reset_n),       // Reset Pin (low active)
 
    .reset_n      (reset_n),       // Reset Pin (low active, asynchronous)
 
    .scg1         (scg1),          // System clock generator 1. Turns off the SMCLK
 
    .scg1         (scg1),          // System clock generator 1. Turns off the SMCLK
 
    .wdt_reset    (wdt_reset)      // Watchdog-timer reset
 
    .wdt_reset    (wdt_reset)      // Watchdog-timer reset
 
);
 
);
 
 
 
 
 
 
 
 
Line 217... Line 227... 
    .nmi_acc      (nmi_acc),       // Non-Maskable interrupt request accepted
 
    .nmi_acc      (nmi_acc),       // Non-Maskable interrupt request accepted
 
    .pc           (pc),            // Program counter
 
    .pc           (pc),            // Program counter
 
    .pc_nxt       (pc_nxt),        // Next PC value (for CALL & IRQ)
 
    .pc_nxt       (pc_nxt),        // Next PC value (for CALL & IRQ)
 
 
 
 
 
// INPUTs
 
// INPUTs
 
 
 
    .cpu_en_s     (cpu_en_s),      // Enable CPU code execution (synchronous)
 
    .cpuoff       (cpuoff),        // Turns off the CPU
 
    .cpuoff       (cpuoff),        // Turns off the CPU
 
    .dbg_halt_cmd (dbg_halt_cmd),  // Halt CPU command
 
    .dbg_halt_cmd (dbg_halt_cmd),  // Halt CPU command
 
    .dbg_reg_sel  (dbg_mem_addr[3:0]), // Debug selected register for rd/wr access
 
    .dbg_reg_sel  (dbg_mem_addr[3:0]), // Debug selected register for rd/wr access
 
    .fe_pmem_wait (fe_pmem_wait),  // Frontend wait for Instruction fetch
 
    .fe_pmem_wait (fe_pmem_wait),  // Frontend wait for Instruction fetch
 
    .gie          (gie),           // General interrupt enable
 
    .gie          (gie),           // General interrupt enable
Line 296... Line 307... 
    .eu_mdb_in    (eu_mdb_in),     // Execution Unit Memory data bus input
 
    .eu_mdb_in    (eu_mdb_in),     // Execution Unit Memory data bus input
 
    .fe_mdb_in    (fe_mdb_in),     // Frontend Memory data bus input
 
    .fe_mdb_in    (fe_mdb_in),     // Frontend Memory data bus input
 
    .fe_pmem_wait (fe_pmem_wait),  // Frontend wait for Instruction fetch
 
    .fe_pmem_wait (fe_pmem_wait),  // Frontend wait for Instruction fetch
 
    .per_addr     (per_addr),      // Peripheral address
 
    .per_addr     (per_addr),      // Peripheral address
 
    .per_din      (per_din),       // Peripheral data input
 
    .per_din      (per_din),       // Peripheral data input
 
    .per_wen      (per_wen),       // Peripheral write enable (high active)
 
    .per_we       (per_we),        // Peripheral write enable (high active)
 
    .per_en       (per_en),        // Peripheral enable (high active)
 
    .per_en       (per_en),        // Peripheral enable (high active)
 
    .pmem_addr    (pmem_addr),     // Program Memory address
 
    .pmem_addr    (pmem_addr),     // Program Memory address
 
    .pmem_cen     (pmem_cen),      // Program Memory chip enable (low active)
 
    .pmem_cen     (pmem_cen),      // Program Memory chip enable (low active)
 
    .pmem_din     (pmem_din),      // Program Memory data input (optional)
 
    .pmem_din     (pmem_din),      // Program Memory data input (optional)
 
    .pmem_wen     (pmem_wen),      // Program Memory write enable (low active) (optional)
 
    .pmem_wen     (pmem_wen),      // Program Memory write enable (low active) (optional)
Line 342... Line 353... 
    .mclk         (mclk),          // Main system clock
 
    .mclk         (mclk),          // Main system clock
 
    .nmi_acc      (nmi_acc),       // Non-Maskable interrupt request accepted
 
    .nmi_acc      (nmi_acc),       // Non-Maskable interrupt request accepted
 
    .per_addr     (per_addr),      // Peripheral address
 
    .per_addr     (per_addr),      // Peripheral address
 
    .per_din      (per_din),       // Peripheral data input
 
    .per_din      (per_din),       // Peripheral data input
 
    .per_en       (per_en),        // Peripheral enable (high active)
 
    .per_en       (per_en),        // Peripheral enable (high active)
 
    .per_wen      (per_wen),       // Peripheral write enable (high active)
 
    .per_we       (per_we),        // Peripheral write enable (high active)
 
    .por          (por),           // Power-on reset
 
    .por          (por),           // Power-on reset
 
    .puc          (puc),           // Main system reset
 
    .puc          (puc),           // Main system reset
 
    .wdtifg_clr   (irq_acc[10]),   // Clear Watchdog-timer interrupt flag
 
    .wdtifg_clr   (irq_acc[10]),   // Clear Watchdog-timer interrupt flag
 
    .wdtifg_set   (wdtifg_set),    // Set Watchdog-timer interrupt flag
 
    .wdtifg_set   (wdtifg_set),    // Set Watchdog-timer interrupt flag
 
    .wdtpw_error  (wdtpw_error),   // Watchdog-timer password error
 
    .wdtpw_error  (wdtpw_error),   // Watchdog-timer password error
Line 374... Line 385... 
    .nmi          (nmi),           // Non-maskable interrupt (asynchronous)
 
    .nmi          (nmi),           // Non-maskable interrupt (asynchronous)
 
    .nmie         (nmie),          // Non-maskable interrupt enable
 
    .nmie         (nmie),          // Non-maskable interrupt enable
 
    .per_addr     (per_addr),      // Peripheral address
 
    .per_addr     (per_addr),      // Peripheral address
 
    .per_din      (per_din),       // Peripheral data input
 
    .per_din      (per_din),       // Peripheral data input
 
    .per_en       (per_en),        // Peripheral enable (high active)
 
    .per_en       (per_en),        // Peripheral enable (high active)
 
    .per_wen      (per_wen),       // Peripheral write enable (high active)
 
    .per_we       (per_we),        // Peripheral write enable (high active)
 
    .puc          (puc),           // Main system reset
 
    .puc          (puc),           // Main system reset
 
    .smclk_en     (smclk_en),      // SMCLK enable
 
    .smclk_en     (smclk_en),      // SMCLK enable
 
    .wdtie        (wdtie)          // Watchdog-timer interrupt enable
 
    .wdtie        (wdtie)          // Watchdog-timer interrupt enable
 
);
 
);
 
 
 
 
Line 395... Line 406... 
// INPUTs
 
// INPUTs
 
    .mclk         (mclk),          // Main system clock
 
    .mclk         (mclk),          // Main system clock
 
    .per_addr     (per_addr),      // Peripheral address
 
    .per_addr     (per_addr),      // Peripheral address
 
    .per_din      (per_din),       // Peripheral data input
 
    .per_din      (per_din),       // Peripheral data input
 
    .per_en       (per_en),        // Peripheral enable (high active)
 
    .per_en       (per_en),        // Peripheral enable (high active)
 
    .per_wen      (per_wen),       // Peripheral write enable (high active)
 
    .per_we       (per_we),        // Peripheral write enable (high active)
 
    .puc          (puc)            // Main system reset
 
    .puc          (puc)            // Main system reset
 
);
 
);
 
`else
 
`else
 
assign per_dout_mpy = 16'h0000;
 
assign per_dout_mpy = 16'h0000;
 
`endif
 
`endif
Line 428... Line 439... 
    .dbg_mem_addr (dbg_mem_addr),  // Debug address for rd/wr access
 
    .dbg_mem_addr (dbg_mem_addr),  // Debug address for rd/wr access
 
    .dbg_mem_dout (dbg_mem_dout),  // Debug unit data output
 
    .dbg_mem_dout (dbg_mem_dout),  // Debug unit data output
 
    .dbg_mem_en   (dbg_mem_en),    // Debug unit memory enable
 
    .dbg_mem_en   (dbg_mem_en),    // Debug unit memory enable
 
    .dbg_mem_wr   (dbg_mem_wr),    // Debug unit memory write
 
    .dbg_mem_wr   (dbg_mem_wr),    // Debug unit memory write
 
    .dbg_reg_wr   (dbg_reg_wr),    // Debug unit CPU register write
 
    .dbg_reg_wr   (dbg_reg_wr),    // Debug unit CPU register write
 
    .dbg_reset    (dbg_reset),     // Reset CPU from debug interface
 
    .dbg_cpu_reset(dbg_cpu_reset), // Reset CPU from debug interface
 
    .dbg_uart_txd (dbg_uart_txd),  // Debug interface: UART TXD
 
    .dbg_uart_txd (dbg_uart_txd),  // Debug interface: UART TXD
 
 
 
 
 
// INPUTs
 
// INPUTs
 
 
 
    .cpu_en_s     (cpu_en_s),      // Enable CPU code execution (synchronous)
 
 
 
    .dbg_clk      (dbg_clk),       // Debug unit clock
 
 
 
    .dbg_en_s     (dbg_en_s),      // Debug interface enable (synchronous)
 
    .dbg_halt_st  (dbg_halt_st),   // Halt/Run status from CPU
 
    .dbg_halt_st  (dbg_halt_st),   // Halt/Run status from CPU
 
    .dbg_mem_din  (dbg_mem_din),   // Debug unit Memory data input
 
    .dbg_mem_din  (dbg_mem_din),   // Debug unit Memory data input
 
    .dbg_reg_din  (dbg_reg_din),   // Debug unit CPU register data input
 
    .dbg_reg_din  (dbg_reg_din),   // Debug unit CPU register data input
 
    .dbg_uart_rxd (dbg_uart_rxd),  // Debug interface: UART RXD
 
    .dbg_rst      (dbg_rst),       // Debug unit reset
 
 
 
    .dbg_uart_rxd (dbg_uart_rxd),  // Debug interface: UART RXD (asynchronous)
 
    .decode_noirq (decode_noirq),  // Frontend decode instruction
 
    .decode_noirq (decode_noirq),  // Frontend decode instruction
 
    .eu_mab       (eu_mab),        // Execution-Unit Memory address bus
 
    .eu_mab       (eu_mab),        // Execution-Unit Memory address bus
 
    .eu_mb_en     (eu_mb_en),      // Execution-Unit Memory bus enable
 
    .eu_mb_en     (eu_mb_en),      // Execution-Unit Memory bus enable
 
    .eu_mb_wr     (eu_mb_wr),      // Execution-Unit Memory bus write transfer
 
    .eu_mb_wr     (eu_mb_wr),      // Execution-Unit Memory bus write transfer
 
    .eu_mdb_in    (eu_mdb_in),     // Memory data bus input
 
    .eu_mdb_in    (eu_mdb_in),     // Memory data bus input
 
    .eu_mdb_out   (eu_mdb_out),    // Memory data bus output
 
    .eu_mdb_out   (eu_mdb_out),    // Memory data bus output
 
    .exec_done    (exec_done),     // Execution completed
 
    .exec_done    (exec_done),     // Execution completed
 
    .fe_mb_en     (fe_mb_en),      // Frontend Memory bus enable
 
    .fe_mb_en     (fe_mb_en),      // Frontend Memory bus enable
 
    .fe_mdb_in    (fe_mdb_in),     // Frontend Memory data bus input
 
    .fe_mdb_in    (fe_mdb_in),     // Frontend Memory data bus input
 
    .mclk         (mclk),          // Main system clock
 
 
 
    .pc           (pc),            // Program counter
 
    .pc           (pc),            // Program counter
 
    .por          (por),           // Power on reset
 
 
 
    .puc          (puc)            // Main system reset
 
    .puc          (puc)            // Main system reset
 
);
 
);
 
 
 
 
 
`else
 
`else
 
assign dbg_freeze   =  1'b0;
 
assign dbg_freeze    =  ~cpu_en_s;
 
assign dbg_halt_cmd =  1'b0;
 
assign dbg_halt_cmd =  1'b0;
 
assign dbg_mem_addr = 16'h0000;
 
assign dbg_mem_addr = 16'h0000;
 
assign dbg_mem_dout = 16'h0000;
 
assign dbg_mem_dout = 16'h0000;
 
assign dbg_mem_en   =  1'b0;
 
assign dbg_mem_en   =  1'b0;
 
assign dbg_mem_wr   =  2'b00;
 
assign dbg_mem_wr   =  2'b00;
 
assign dbg_reg_wr   =  1'b0;
 
assign dbg_reg_wr   =  1'b0;
 
assign dbg_reset    =  1'b0;
 
assign dbg_cpu_reset =  1'b0;
 
assign dbg_uart_txd =  1'b0;
 
assign dbg_uart_txd =  1'b0;
 
`endif
 
`endif
 
 
 
 
 
 
 
 
 
endmodule // openMSP430
 
endmodule // openMSP430

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.