| Line 29... |
Line 29... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 103 $
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// $Rev: 106 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
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// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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//`define OMSP_NO_INCLUDE
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//`define OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_undefines.v"
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`include "openMSP430_undefines.v"
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| Line 111... |
Line 111... |
`define DBG_HWBRK_0
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`define DBG_HWBRK_0
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`define DBG_HWBRK_1
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`define DBG_HWBRK_1
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`define DBG_HWBRK_2
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`define DBG_HWBRK_2
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`define DBG_HWBRK_3
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`define DBG_HWBRK_3
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|
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// Defines the debugger CPU_CTL.RST_BRK_EN reset value (CPU break on PUC reset)
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//
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// When defined, this concretely bring the CPU to break after a PUC
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// occurrence by default. This is typically usefull when the program
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// memory can only be initialized through the serial debug interface.
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//
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//`define DBG_RST_BRK_EN
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//==========================================================================//
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//==========================================================================//
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//==========================================================================//
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//==========================================================================//
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//==========================================================================//
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//==========================================================================//
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//==========================================================================//
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//==========================================================================//
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| Line 364... |
Line 372... |
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// Basic clock module: BCSCTL2 Control Register
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// Basic clock module: BCSCTL2 Control Register
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`define SELS 3
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`define SELS 3
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`define DIVSx 2:1
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`define DIVSx 2:1
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|
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// Timer A: TACTL Control Register
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`define TASSELx 9:8
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`define TAIDx 7:6
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`define TAMCx 5:4
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`define TACLR 2
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`define TAIE 1
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`define TAIFG 0
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// Timer A: TACCTLx Capture/Compare Control Register
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`define TACMx 15:14
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`define TACCISx 13:12
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`define TASCS 11
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`define TASCCI 10
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`define TACAP 8
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`define TAOUTMODx 7:5
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`define TACCIE 4
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`define TACCI 3
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`define TAOUT 2
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`define TACOV 1
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`define TACCIFG 0
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//
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//
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// DEBUG INTERFACE EXTRA CONFIGURATION
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// DEBUG INTERFACE EXTRA CONFIGURATION
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//======================================
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//======================================
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