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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [openMSP430_undefines.v] - Diff between revs 154 and 180
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Rev 154 |
Rev 180 |
Line 261... |
Line 261... |
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
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// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// ASIC/FPGA-like clocking
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`ifdef ASIC_CLOCKING
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`undef ASIC_CLOCKING
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`endif
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// Fine grained clock gating
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// Fine grained clock gating
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`ifdef CLOCK_GATING
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`ifdef CLOCK_GATING
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`undef CLOCK_GATING
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`undef CLOCK_GATING
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`endif
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`endif
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