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Line 29... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 103 $
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// $Rev: 106 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
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// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_TA_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "omsp_timerA_defines.v"
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`endif
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`endif
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module omsp_timerA (
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module omsp_timerA (
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// OUTPUTs
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// OUTPUTs
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irq_ta0_acc, // Interrupt request TACCR0 accepted
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irq_ta0_acc, // Interrupt request TACCR0 accepted
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mclk, // Main system clock
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mclk, // Main system clock
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per_addr, // Peripheral address
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per_addr, // Peripheral address
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per_din, // Peripheral data input
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per_din, // Peripheral data input
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per_en, // Peripheral enable (high active)
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per_en, // Peripheral enable (high active)
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per_wen, // Peripheral write enable (high active)
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per_we, // Peripheral write enable (high active)
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puc, // Main system reset
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puc, // Main system reset
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smclk_en, // SMCLK enable (from CPU)
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smclk_en, // SMCLK enable (from CPU)
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ta_cci0a, // Timer A capture 0 input A
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ta_cci0a, // Timer A capture 0 input A
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ta_cci0b, // Timer A capture 0 input B
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ta_cci0b, // Timer A capture 0 input B
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ta_cci1a, // Timer A capture 1 input A
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ta_cci1a, // Timer A capture 1 input A
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input irq_ta0_acc; // Interrupt request TACCR0 accepted
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input irq_ta0_acc; // Interrupt request TACCR0 accepted
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input mclk; // Main system clock
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input mclk; // Main system clock
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input [7:0] per_addr; // Peripheral address
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input [7:0] per_addr; // Peripheral address
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input [15:0] per_din; // Peripheral data input
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input [15:0] per_din; // Peripheral data input
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input per_en; // Peripheral enable (high active)
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input per_en; // Peripheral enable (high active)
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input [1:0] per_wen; // Peripheral write enable (high active)
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input [1:0] per_we; // Peripheral write enable (high active)
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input puc; // Main system reset
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input puc; // Main system reset
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input smclk_en; // SMCLK enable (from CPU)
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input smclk_en; // SMCLK enable (from CPU)
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input ta_cci0a; // Timer A capture 0 input A
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input ta_cci0a; // Timer A capture 0 input A
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input ta_cci0b; // Timer A capture 0 input B
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input ta_cci0b; // Timer A capture 0 input B
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input ta_cci1a; // Timer A capture 1 input A
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input ta_cci1a; // Timer A capture 1 input A
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TAIV : reg_dec = TAIV_D;
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TAIV : reg_dec = TAIV_D;
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default: reg_dec = {512{1'b0}};
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default: reg_dec = {512{1'b0}};
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endcase
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endcase
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// Read/Write probes
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// Read/Write probes
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wire reg_write = |per_wen & per_en;
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wire reg_write = |per_we & per_en;
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wire reg_read = ~|per_wen & per_en;
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wire reg_read = ~|per_we & per_en;
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// Read/Write vectors
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// Read/Write vectors
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wire [511:0] reg_wr = reg_dec & {512{reg_write}};
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wire [511:0] reg_wr = reg_dec & {512{reg_write}};
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wire [511:0] reg_rd = reg_dec & {512{reg_read}};
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wire [511:0] reg_rd = reg_dec & {512{reg_read}};
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(tacctl2[`TACCIFG] & tacctl2[`TACCIE]);
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(tacctl2[`TACCIFG] & tacctl2[`TACCIE]);
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endmodule // omsp_timerA
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endmodule // omsp_timerA
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_TA_NO_INCLUDE
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`else
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`else
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`include "openMSP430_undefines.v"
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`include "omsp_timerA_undefines.v"
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`endif
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`endif
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No newline at end of file
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No newline at end of file
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