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Line 28... |
/* */
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/* */
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/* Author(s): */
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/* Author(s): */
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/* - Olivier Girard, olgirard@gmail.com */
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/* - Olivier Girard, olgirard@gmail.com */
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/* */
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/* */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* $Rev: 19 $ */
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/* $Rev: 106 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
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/* $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $ */
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/*===========================================================================*/
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/*===========================================================================*/
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`define LONG_TIMEOUT
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`define LONG_TIMEOUT
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integer mclk_counter;
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integer mclk_counter;
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Line 47... |
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integer smclk_counter;
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integer smclk_counter;
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always @ (negedge mclk)
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always @ (negedge mclk)
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if (smclk_en) smclk_counter <= smclk_counter+1;
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if (smclk_en) smclk_counter <= smclk_counter+1;
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reg [15:0] reg_val;
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initial
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initial
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begin
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begin
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$display(" ===============================================");
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$display(" ===============================================");
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$display("| START SIMULATION |");
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$display("| START SIMULATION |");
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repeat(600) @(posedge mclk);
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repeat(600) @(posedge mclk);
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if (mclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) =====");
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if (mclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) =====");
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if (smclk_counter !== 75) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) =====");
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if (smclk_counter !== 75) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) =====");
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// SMCLK GENERATION - DCO_CLK INPUT
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//--------------------------------------------------------
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@(r15 === 16'h3000);
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repeat(50) @(posedge mclk);
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if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 1) =====");
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cpu_en = 1'b0;
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repeat(3) @(posedge mclk);
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reg_val = r14; // Read R14 register & initialize aclk/smclk counters
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aclk_counter = 0;
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smclk_counter = 0;
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if (dbg_freeze !== 1'b1) tb_error("====== DBG_FREEZE signal is not active (test 2) =====");
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repeat(500) @(posedge mclk); // Make sure that the CPU is stopped
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if (reg_val !== r14) tb_error("====== CPU is not stopped (test 3) =====");
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if (aclk_counter !== 0) tb_error("====== ACLK is not stopped (test 4) =====");
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if (smclk_counter !== 0) tb_error("====== SMCLK is not stopped (test 5) =====");
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if (dbg_freeze !== 1'b1) tb_error("====== DBG_FREEZE signal is not active (test 6) =====");
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cpu_en = 1'b1;
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repeat(500) @(posedge mclk); // Make sure that the CPU runs again
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if (reg_val == r14) tb_error("====== CPU is not running (test 7) =====");
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if (aclk_counter == 0) tb_error("====== ACLK is not running (test 8) =====");
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if (smclk_counter == 0) tb_error("====== SMCLK is not running (test 9) =====");
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if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 10) =====");
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stimulus_done = 1;
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stimulus_done = 1;
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end
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end
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No newline at end of file
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No newline at end of file
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