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| Rev 134 |
Rev 180 |
| Line 74... |
Line 74... |
repeat(5) @(posedge mclk);
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repeat(5) @(posedge mclk);
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stimulus_done = 0;
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stimulus_done = 0;
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force tb_openMSP430.dut.wdt_reset = 1'b0;
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force tb_openMSP430.dut.wdt_reset = 1'b0;
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`ifdef ASIC
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`ifdef ASIC_CLOCKING
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// MCLK GENERATION: SELECTING DCO_CLK
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// MCLK GENERATION: SELECTING DCO_CLK
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//--------------------------------------------------------
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//--------------------------------------------------------
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// ------- Divider /1 ----------
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// ------- Divider /1 ----------
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| Line 531... |
Line 531... |
//--------------------------------------------------------
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//--------------------------------------------------------
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bcsctl1_mask = 16'h0000;
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bcsctl1_mask = 16'h0000;
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bcsctl2_mask = 16'h0000;
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bcsctl2_mask = 16'h0000;
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`ifdef ASIC
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`ifdef ASIC_CLOCKING
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`ifdef ACLK_DIVIDER
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`ifdef ACLK_DIVIDER
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bcsctl1_mask = bcsctl1_mask | 16'h0030;
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bcsctl1_mask = bcsctl1_mask | 16'h0030;
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`endif
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`endif
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`else
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`else
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bcsctl1_mask = bcsctl1_mask | 16'h0030;
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bcsctl1_mask = bcsctl1_mask | 16'h0030;
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| Line 545... |
Line 545... |
bcsctl2_mask = bcsctl2_mask | 16'h0080;
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bcsctl2_mask = bcsctl2_mask | 16'h0080;
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`endif
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`endif
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`ifdef MCLK_DIVIDER
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`ifdef MCLK_DIVIDER
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bcsctl2_mask = bcsctl2_mask | 16'h0030;
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bcsctl2_mask = bcsctl2_mask | 16'h0030;
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`endif
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`endif
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`ifdef ASIC
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`ifdef ASIC_CLOCKING
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`ifdef SMCLK_MUX
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`ifdef SMCLK_MUX
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bcsctl2_mask = bcsctl2_mask | 16'h0008;
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bcsctl2_mask = bcsctl2_mask | 16'h0008;
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`endif
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`endif
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`ifdef SMCLK_DIVIDER
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`ifdef SMCLK_DIVIDER
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bcsctl2_mask = bcsctl2_mask | 16'h0006;
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bcsctl2_mask = bcsctl2_mask | 16'h0006;
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