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Line 30... |
/* */
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/* */
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/* Author(s): */
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/* Author(s): */
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/* - Olivier Girard, olgirard@gmail.com */
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/* - Olivier Girard, olgirard@gmail.com */
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/* */
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/* */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* $Rev: 95 $ */
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/* $Rev: 106 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */
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/* $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $ */
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/*===========================================================================*/
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/*===========================================================================*/
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`define LONG_TIMEOUT
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`define LONG_TIMEOUT
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reg [15:0] dbg_id_pmem;
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reg [15:0] dbg_id_pmem;
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Line 46... |
initial
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initial
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begin
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begin
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$display(" ===============================================");
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$display(" ===============================================");
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$display("| START SIMULATION |");
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$display("| START SIMULATION |");
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$display(" ===============================================");
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$display(" ===============================================");
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#1 dbg_en = 1;
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repeat(30) @(posedge mclk);
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repeat(30) @(posedge mclk);
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stimulus_done = 0;
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stimulus_done = 0;
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// SEND UART SYNCHRONIZATION FRAME
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// SEND UART SYNCHRONIZATION FRAME
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dbg_uart_tx(DBG_SYNC);
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dbg_uart_tx(DBG_SYNC);
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`ifdef DBG_RST_BRK_EN
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dbg_uart_wr(CPU_CTL, 16'h0002); // RUN
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`endif
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// TEST CPU REGISTERS
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// TEST CPU REGISTERS
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//--------------------------------------------------------
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//--------------------------------------------------------
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dbg_id_pmem = `PMEM_SIZE;
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dbg_id_pmem = `PMEM_SIZE;
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dbg_id_dmem = `DMEM_SIZE;
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dbg_id_dmem = `DMEM_SIZE;
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dbg_id = {dbg_id_pmem, dbg_id_dmem};
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dbg_id = {dbg_id_pmem, dbg_id_dmem};
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