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Line 30... |
/* */
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/* */
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/* Author(s): */
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/* Author(s): */
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/* - Olivier Girard, olgirard@gmail.com */
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/* - Olivier Girard, olgirard@gmail.com */
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/* */
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/* */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* $Rev: 111 $ */
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/* $Rev: 134 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ */
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/* $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $ */
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/*===========================================================================*/
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/*===========================================================================*/
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`define LONG_TIMEOUT
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`define LONG_TIMEOUT
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reg [2:0] cpu_version;
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reg [2:0] cpu_version;
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Line 335... |
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dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0000)); // select @0x0200
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dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0000)); // select @0x0200
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dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
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dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
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dbg_uart_wr(MEM_CTL, 16'h0001); // Start burst to 16 bit registers read
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dbg_uart_wr(MEM_CTL, 16'h0001); // Start burst to 16 bit registers read
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dbg_uart_rx16(); // read 1st data
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dbg_uart_rx16; // read 1st data
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if (dbg_uart_buf !== 16'h1234) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 1st DATA =====");
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if (dbg_uart_buf !== 16'h1234) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 1st DATA =====");
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dbg_uart_rx16(); // read 2nd data
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dbg_uart_rx16; // read 2nd data
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if (dbg_uart_buf !== 16'h5678) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 2nd DATA =====");
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if (dbg_uart_buf !== 16'h5678) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 2nd DATA =====");
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dbg_uart_rx16(); // read 3rd data
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dbg_uart_rx16; // read 3rd data
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if (dbg_uart_buf !== 16'h9abc) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 3rd DATA =====");
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if (dbg_uart_buf !== 16'h9abc) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 3rd DATA =====");
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dbg_uart_rx16(); // read 4th data
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dbg_uart_rx16; // read 4th data
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if (dbg_uart_buf !== 16'hdef0) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 4th DATA =====");
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if (dbg_uart_buf !== 16'hdef0) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 4th DATA =====");
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dbg_uart_rx16(); // read 5th data
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dbg_uart_rx16; // read 5th data
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if (dbg_uart_buf !== 16'h0fed) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 5th DATA =====");
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if (dbg_uart_buf !== 16'h0fed) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 5th DATA =====");
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// TEST 16B WRITE BURSTS (CPU REGISTERS)
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// TEST 16B WRITE BURSTS (CPU REGISTERS)
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//--------------------------------------------------------
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//--------------------------------------------------------
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Line 374... |
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dbg_uart_wr(MEM_ADDR, 16'h0005); // select @0x0200
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dbg_uart_wr(MEM_ADDR, 16'h0005); // select @0x0200
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dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
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dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
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dbg_uart_wr(MEM_CTL, 16'h0005); // Start burst to 16 bit cpu registers read
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dbg_uart_wr(MEM_CTL, 16'h0005); // Start burst to 16 bit cpu registers read
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dbg_uart_rx16(); // read 1st data
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dbg_uart_rx16; // read 1st data
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if (dbg_uart_buf !== 16'hcba9) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 1st DATA =====");
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if (dbg_uart_buf !== 16'hcba9) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 1st DATA =====");
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dbg_uart_rx16(); // read 2nd data
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dbg_uart_rx16; // read 2nd data
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if (dbg_uart_buf !== 16'h8765) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 2nd DATA =====");
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if (dbg_uart_buf !== 16'h8765) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 2nd DATA =====");
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dbg_uart_rx16(); // read 3rd data
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dbg_uart_rx16; // read 3rd data
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if (dbg_uart_buf !== 16'h4321) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 3rd DATA =====");
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if (dbg_uart_buf !== 16'h4321) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 3rd DATA =====");
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dbg_uart_rx16(); // read 4th data
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dbg_uart_rx16; // read 4th data
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if (dbg_uart_buf !== 16'h0123) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 4th DATA =====");
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if (dbg_uart_buf !== 16'h0123) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 4th DATA =====");
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dbg_uart_rx16(); // read 5th data
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dbg_uart_rx16; // read 5th data
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if (dbg_uart_buf !== 16'h4567) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 5th DATA =====");
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if (dbg_uart_buf !== 16'h4567) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 5th DATA =====");
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// TEST 8B WRITE BURSTS (MEMORY)
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// TEST 8B WRITE BURSTS (MEMORY)
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//--------------------------------------------------------
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//--------------------------------------------------------
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Line 413... |
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dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0000)); // select @0x0200
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dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0000)); // select @0x0200
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dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
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dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
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dbg_uart_wr(MEM_CTL, 16'h0009); // Start burst to 8 bit registers read
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dbg_uart_wr(MEM_CTL, 16'h0009); // Start burst to 8 bit registers read
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dbg_uart_rx8(); // read 1st data
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dbg_uart_rx8; // read 1st data
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if (dbg_uart_buf !== 16'h0091) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 1st DATA =====");
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if (dbg_uart_buf !== 16'h0091) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 1st DATA =====");
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dbg_uart_rx8(); // read 2nd data
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dbg_uart_rx8; // read 2nd data
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if (dbg_uart_buf !== 16'h0082) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 2nd DATA =====");
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if (dbg_uart_buf !== 16'h0082) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 2nd DATA =====");
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dbg_uart_rx8(); // read 3rd data
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dbg_uart_rx8; // read 3rd data
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if (dbg_uart_buf !== 16'h0073) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 3rd DATA =====");
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if (dbg_uart_buf !== 16'h0073) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 3rd DATA =====");
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dbg_uart_rx8(); // read 4th data
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dbg_uart_rx8; // read 4th data
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if (dbg_uart_buf !== 16'h0064) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 4th DATA =====");
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if (dbg_uart_buf !== 16'h0064) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 4th DATA =====");
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dbg_uart_rx8(); // read 5th data
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dbg_uart_rx8; // read 5th data
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if (dbg_uart_buf !== 16'h0055) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 5th DATA =====");
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if (dbg_uart_buf !== 16'h0055) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 5th DATA =====");
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