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https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
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| Rev 134 |
Rev 154 |
| Line 41... |
Line 41... |
reg mpy_info;
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reg mpy_info;
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reg [8:0] dmem_size;
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reg [8:0] dmem_size;
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reg [5:0] pmem_size;
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reg [5:0] pmem_size;
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reg [31:0] dbg_id;
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reg [31:0] dbg_id;
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// Set oMSP parameters for later check
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defparam dut.INST_NR = 8'h12;
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defparam dut.TOTAL_NR = 8'h34;
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initial
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initial
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begin
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begin
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$display(" ===============================================");
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$display(" ===============================================");
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$display("| START SIMULATION |");
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$display("| START SIMULATION |");
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$display(" ===============================================");
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$display(" ===============================================");
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| Line 200... |
Line 204... |
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@(r15 === 16'h5003);
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@(r15 === 16'h5003);
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if (r10 !== dbg_id[15:0]) tb_error("====== CPU_ID_LO incorrect (test 5) =====");
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if (r10 !== dbg_id[15:0]) tb_error("====== CPU_ID_LO incorrect (test 5) =====");
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if (r11 !== dbg_id[31:16]) tb_error("====== CPU_ID_HI incorrect (test 6) =====");
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if (r11 !== dbg_id[31:16]) tb_error("====== CPU_ID_HI incorrect (test 6) =====");
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// READ/WRITE CPU_NR
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//------------------------------
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@(r15 === 16'h6000);
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@(r15 === 16'h6001);
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if (r10 !== 16'h3412) tb_error("====== CPU_NR incorrect (test 1) =====");
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@(r15 === 16'h6002);
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if (r10 !== 16'h3412) tb_error("====== CPU_NR incorrect (test 2) =====");
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@(r15 === 16'h6003);
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if (r10 !== 16'h3412) tb_error("====== CPU_NR incorrect (test 3) =====");
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stimulus_done = 1;
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stimulus_done = 1;
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end
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end
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