OpenCores

Rev 111	Rev 134
Line 28...	Line 28...
`/* */`	`/* */`
`/* Author(s): */`	`/* Author(s): */`
`/* - Olivier Girard, olgirard@gmail.com */`	`/* - Olivier Girard, olgirard@gmail.com */`
`/* */`	`/* */`
`/---------------------------------------------------------------------------/`	`/---------------------------------------------------------------------------/`
`/* $Rev: 111 $ */`	`/* $Rev: 134 $ */`
`/* $LastChangedBy: olivier.girard $ */`	`/* $LastChangedBy: olivier.girard $ */`
`/* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ */`	`/* $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $ */`
`/===========================================================================/`	`/===========================================================================/`

`.global main`	`.global main`

`.set DMEM_BASE, (__data_start )`	`.set DMEM_BASE, (__data_start )`
Line 57...	Line 57...
`mov &WDTCTL, r6`	`mov &WDTCTL, r6`
`mov #0x5aaa, &WDTCTL`	`mov #0x5aaa, &WDTCTL`
`mov &WDTCTL, r7`	`mov &WDTCTL, r7`
`mov #0x5a00, &WDTCTL`	`mov #0x5a00, &WDTCTL`
`mov &WDTCTL, r8`	`mov &WDTCTL, r8`
	`mov &IFG1, r9`
	`mov.b #0x00, &IFG1`

`mov #0x1000, r15`	`mov #0x1000, r15`


`/* -------------- WATCHDOG TEST: INTERVAL MODE /64 ------------ */`	`/* -------------- WATCHDOG TEST: INTERVAL MODE /64 ------------ */`
Line 82...	Line 84...



`bic.b #0x01, &IE1 ;# Disable watchdog interrupt`	`bic.b #0x01, &IE1 ;# Disable watchdog interrupt`

`mov #0x5a1b, &WDTCTL ;# Enable interval mode /64 & clear counter`	`mov #0x0205, r4`
	`mov &WDTCTL, r5 ;# Check if ACLK is selected`
	`bit #0x0004, r5`
	`jnz aclk_sel_64`
	`mov #0x0012, r4`
	`aclk_sel_64:`

`mov #0x0010, r4`	`mov #0x5a1b, &WDTCTL ;# Enable interval mode /64 & clear counter`
`mov #0x0002, r5`	`mov #0x0002, r5`

`wait_loop_64_no_irq:`	`wait_loop_64_no_irq:`
`dec r4`	`dec r4`
`cmp #0x0000, r4`	`cmp #0x0000, r4`
`jne wait_loop_64_no_irq`	`jne wait_loop_64_no_irq`

Line 99...	Line 107...
`mov &IFG1, r8`	`mov &IFG1, r8`

`mov #0x2001, r15`	`mov #0x2001, r15`



`mov #0x5a9b, &WDTCTL ;# Enable interval mode /64 & clear counter & enable hold`	`mov #0x5a9b, &WDTCTL ;# Enable interval mode /64 & clear counter & enable hold`

`mov #0x0020, r4`	`mov #0x0020, r4`
`mov #0x0022, r5`	`mov #0x0022, r5`
`wait_loop_64_no_irq_hold:`	`wait_loop_64_no_irq_hold:`

Line 28...

/*                                                                           */

/*                                                                           */

/* Author(s):                                                                */

/* Author(s):                                                                */

/*             - Olivier Girard,    olgirard@gmail.com                       */

/*             - Olivier Girard,    olgirard@gmail.com                       */

/*                                                                           */

/*                                                                           */

/*---------------------------------------------------------------------------*/

/*---------------------------------------------------------------------------*/

/* $Rev: 111 $                                                                */

/* $Rev: 134 $                                                                */

/* $LastChangedBy: olivier.girard $                                          */

/* $LastChangedBy: olivier.girard $                                          */

/* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $          */

/* $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $          */

/*===========================================================================*/

/*===========================================================================*/

.global main

.global main

.set   DMEM_BASE, (__data_start     )

.set   DMEM_BASE, (__data_start     )

Line 57...

        mov  &WDTCTL, r6

        mov  &WDTCTL, r6

        mov  #0x5aaa, &WDTCTL

        mov  #0x5aaa, &WDTCTL

        mov  &WDTCTL, r7

        mov  &WDTCTL, r7

        mov  #0x5a00, &WDTCTL

        mov  #0x5a00, &WDTCTL

        mov  &WDTCTL, r8

        mov  &WDTCTL, r8

        mov   &IFG1,   r9

        mov.b #0x00,   &IFG1

        mov  #0x1000, r15

        mov  #0x1000, r15

        /* --------------   WATCHDOG TEST:  INTERVAL MODE /64  ------------ */

        /* --------------   WATCHDOG TEST:  INTERVAL MODE /64  ------------ */

Line 82...

Line 84...

        bic.b #0x01,   &IE1	  ;# Disable watchdog interrupt

        bic.b #0x01,   &IE1	  ;# Disable watchdog interrupt

        mov   #0x5a1b, &WDTCTL	  ;# Enable interval mode /64 & clear counter

        mov   #0x0205, r4

        mov   &WDTCTL, r5	  ;# Check if ACLK is selected

        bit   #0x0004, r5

        jnz   aclk_sel_64

        mov   #0x0012, r4

   aclk_sel_64:

        mov   #0x0010, r4

        mov   #0x5a1b, &WDTCTL	  ;# Enable interval mode /64 & clear counter

        mov   #0x0002, r5

        mov   #0x0002, r5

wait_loop_64_no_irq:

wait_loop_64_no_irq:

        dec   r4

        dec   r4

        cmp   #0x0000, r4

        cmp   #0x0000, r4

        jne   wait_loop_64_no_irq

        jne   wait_loop_64_no_irq

Line 99...

Line 107...

        mov    &IFG1, r8

        mov    &IFG1, r8

        mov   #0x2001, r15

        mov   #0x2001, r15

        mov   #0x5a9b, &WDTCTL	  ;# Enable interval mode /64 & clear counter & enable hold

        mov   #0x5a9b, &WDTCTL	  ;# Enable interval mode /64 & clear counter & enable hold

        mov   #0x0020, r4

        mov   #0x0020, r4

        mov   #0x0022, r5

        mov   #0x0022, r5

wait_loop_64_no_irq_hold:

wait_loop_64_no_irq_hold:

Browse

Tools

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [wdt_interval.s43] - Diff between revs 111 and 134