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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [wdt_wkup.v] - Diff between revs 134 and 180

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Rev 134 Rev 180
Line 48... Line 48...
integer smclk_cnt;
integer smclk_cnt;
always @(negedge smclk)
always @(negedge smclk)
  smclk_cnt <= smclk_cnt+1;
  smclk_cnt <= smclk_cnt+1;
 
 
integer aclk_cnt;
integer aclk_cnt;
`ifdef ASIC
`ifdef ASIC_CLOCKING
always @(negedge aclk)
always @(negedge aclk)
  aclk_cnt <= aclk_cnt+1;
  aclk_cnt <= aclk_cnt+1;
`else
`else
always @(negedge lfxt_clk)
always @(negedge lfxt_clk)
  aclk_cnt <= aclk_cnt+1;
  aclk_cnt <= aclk_cnt+1;
Line 61... Line 61...
integer inst_cnt;
integer inst_cnt;
always @(inst_number)
always @(inst_number)
  inst_cnt <= inst_cnt+1;
  inst_cnt <= inst_cnt+1;
 
 
reg watchdog_clock;
reg watchdog_clock;
`ifdef ASIC
`ifdef ASIC_CLOCKING
  `ifdef WATCHDOG_MUX
  `ifdef WATCHDOG_MUX
       always @(posedge lfxt_clk or negedge lfxt_clk) watchdog_clock <= lfxt_clk;
       always @(posedge lfxt_clk or negedge lfxt_clk) watchdog_clock <= lfxt_clk;
  `else
  `else
    `ifdef WATCHDOG_NOMUX_ACLK
    `ifdef WATCHDOG_NOMUX_ACLK
       always @(posedge lfxt_clk or negedge lfxt_clk) watchdog_clock <= lfxt_clk;
       always @(posedge lfxt_clk or negedge lfxt_clk) watchdog_clock <= lfxt_clk;
Line 104... Line 104...
      // WATCHDOG TEST:  INTERVAL MODE /64
      // WATCHDOG TEST:  INTERVAL MODE /64
      //--------------------------------------------------------
      //--------------------------------------------------------
 
 
      @(r15==16'h1000);
      @(r15==16'h1000);
 
 
`ifdef ASIC
`ifdef ASIC_CLOCKING
  `ifdef WATCHDOG_MUX
  `ifdef WATCHDOG_MUX
    `ifdef ACLK_DIVIDER
    `ifdef ACLK_DIVIDER
      repeat(5) @(posedge watchdog_clock);
      repeat(5) @(posedge watchdog_clock);
    `else
    `else
      repeat(4) @(posedge watchdog_clock);
      repeat(4) @(posedge watchdog_clock);
Line 133... Line 133...
           dco_clk_cnt = 0;
           dco_clk_cnt = 0;
           mclk_cnt    = 0;
           mclk_cnt    = 0;
           smclk_cnt   = 0;
           smclk_cnt   = 0;
           aclk_cnt    = 0;
           aclk_cnt    = 0;
           inst_cnt    = 0;
           inst_cnt    = 0;
           `ifdef ASIC
           `ifdef ASIC_CLOCKING
             `ifdef WATCHDOG_MUX
             `ifdef WATCHDOG_MUX
                 repeat(62) @(posedge watchdog_clock);
                 repeat(62) @(posedge watchdog_clock);
                 jj = 2;
                 jj = 2;
                 if (dco_clk_cnt !==  0)   tb_error("====== DCO_CLK is running                     (CONFIG 1) =====");
                 if (dco_clk_cnt !==  0)   tb_error("====== DCO_CLK is running                     (CONFIG 1) =====");
                 if (mclk_cnt    !==  0)   tb_error("====== MCLK    is running                     (CONFIG 1) =====");
                 if (mclk_cnt    !==  0)   tb_error("====== MCLK    is running                     (CONFIG 1) =====");

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