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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src-c/] [dhrystone_v2.1/] [dhrystone_v2.1.v] - Diff between revs 145 and 200

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Rev 145 Rev 200
Line 19... Line 19...
/* You should have received a copy of the GNU Lesser General Public License  */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*                                                                           */
/*===========================================================================*/
/*===========================================================================*/
/*                                 SANDBOX                                   */
/*                              DHRYSTONE V2.1                               */
/*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/*                                                                           */
/*                                                                           */
/* Author(s):                                                                */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*                                                                           */
Line 52... Line 52...
 
 
      //---------------------------------------
      //---------------------------------------
      // Check CPU configuration
      // Check CPU configuration
      //---------------------------------------
      //---------------------------------------
 
 
      if ((`PMEM_SIZE !== 24576) || (`DMEM_SIZE !== 16384))
      if ((`PMEM_SIZE !== 49152) || (`DMEM_SIZE !== 10240))
        begin
        begin
           $display(" ===============================================");
           $display(" ===============================================");
           $display("|               SIMULATION ERROR                |");
           $display("|               SIMULATION ERROR                |");
           $display("|                                               |");
           $display("|                                               |");
           $display("|  Core must be configured for:                 |");
           $display("|  Core must be configured for:                 |");
           $display("|               - 24kB program memory           |");
           $display("|               - 48kB program memory           |");
           $display("|               - 16kB data memory              |");
           $display("|               - 10kB data memory              |");
           $display(" ===============================================");
           $display(" ===============================================");
           $finish;
           $finish;
        end
        end
 
 
 
      // Disable watchdog
 
      // (only required because RedHat/TI GCC toolchain doesn't disable watchdog properly at startup)
 
      `ifdef WATCHDOG
 
        force dut.watchdog_0.wdtcnt   = 16'h0000;
 
      `endif
 
 
      //---------------------------------------
      //---------------------------------------
      // Number of benchmark iteration
      // Number of benchmark iteration
      // (Must match the C-code value)
      // (Must match the C-code value)
      //---------------------------------------
      //---------------------------------------
 
 
Line 95... Line 101...
      // Detect beginning of run
      // Detect beginning of run
      @(posedge p3_dout[0]);
      @(posedge p3_dout[0]);
      dhry_start_time = $time;
      dhry_start_time = $time;
      $timeformat(-3, 3, " ms", 10);
      $timeformat(-3, 3, " ms", 10);
      $display("\nINFO-VERILOG: Dhrystone loop started at %t ", dhry_start_time);
      $display("\nINFO-VERILOG: Dhrystone loop started at %t ", dhry_start_time);
 
      $display("");
 
      $display("INFO-VERILOG: Be patient... there could be up to 16ms to simulate");
 
      $display("");
 
 
      // Detect end of run
      // Detect end of run
      @(negedge p3_dout[0]);
      @(negedge p3_dout[0]);
      dhry_end_time = $time;
      dhry_end_time = $time;
      $timeformat(-3, 3, " ms", 10);
      $timeformat(-3, 3, " ms", 10);
Line 132... Line 141...
 
 
// Display stuff from the C-program
// Display stuff from the C-program
always @(p2_dout[0])
always @(p2_dout[0])
  begin
  begin
     $write("%s", p1_dout);
     $write("%s", p1_dout);
 
     $fflush();
 
  end
 
 
 
// Display some info to show simulation progress
 
initial
 
  begin
 
     @(posedge p3_dout[0]);
 
     #1000000;
 
     while (p3_dout[0])
 
       begin
 
          $display("INFO-VERILOG: Simulated time %t ", $time);
 
          #1000000;
 
       end
  end
  end
 
 
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