| Line 28... |
Line 28... |
# Author(s):
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# Author(s):
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# - Olivier Girard, olgirard@gmail.com
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# - Olivier Girard, olgirard@gmail.com
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# - Mihai M., mmihai@delajii.net
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# - Mihai M., mmihai@delajii.net
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#
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#
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#------------------------------------------------------------------------------
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#------------------------------------------------------------------------------
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# $Rev: 138 $
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# $Rev: 73 $
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# $LastChangedBy: olivier.girard $
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# $LastChangedBy: olivier.girard $
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# $LastChangedDate: 2012-04-23 13:10:00 +0200 (Mon, 23 Apr 2012) $
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# $LastChangedDate: 2010-08-03 12:26:39 -0700 (Tue, 03 Aug 2010) $
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#------------------------------------------------------------------------------
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#------------------------------------------------------------------------------
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|
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###############################################################################
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###############################################################################
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# Parameter Check #
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# Parameter Check #
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###############################################################################
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###############################################################################
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| Line 80... |
Line 80... |
iverilog -o simv -c $3 -D NODUMP
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iverilog -o simv -c $3 -D NODUMP
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else
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else
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iverilog -o simv -c $3
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iverilog -o simv -c $3
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fi
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fi
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|
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if [ `uname -o` = "Cygwin" ]
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if [[ $(uname -s) == CYGWIN* ]];
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then
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then
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vvp.exe ./simv
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vvp.exe ./simv
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else
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else
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./simv
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./simv
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fi
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fi
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| Line 103... |
Line 103... |
vargs="$vargs +define+VXL +define+CVER" ;;
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vargs="$vargs +define+VXL +define+CVER" ;;
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verilog* )
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verilog* )
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vargs="$vargs +define+VXL" ;;
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vargs="$vargs +define+VXL" ;;
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ncverilog* )
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ncverilog* )
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rm -rf INCA_libs
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rm -rf INCA_libs
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vargs="$vargs +access+r +nclicq +ncinput+../bin/cov_ncverilog.tcl -covdut openMSP430 -covfile ../bin/cov_ncverilog.ccf -coverage all +define+TRN_FILE" ;;
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#vargs="$vargs +access+r +nclicq +ncinput+../bin/cov_ncverilog.tcl -covdut openMSP430 -covfile ../bin/cov_ncverilog.ccf -coverage all +define+TRN_FILE" ;;
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vargs="$vargs +access+r +nclicq +define+TRN_FILE" ;;
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vcs* )
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vcs* )
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rm -rf csrc simv*
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rm -rf csrc simv*
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vargs="$vargs -R -debug_pp +vcs+lic+wait +v2k +define+VPD_FILE" ;;
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vargs="$vargs -R -debug_pp +vcs+lic+wait +v2k +define+VPD_FILE" ;;
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vsim* )
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vsim* )
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# Modelsim
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# Modelsim
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| Line 115... |
Line 116... |
vlib work
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vlib work
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exec vlog +acc=prn -f $3 $vargs -R -c -do "run -all" ;;
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exec vlog +acc=prn -f $3 $vargs -R -c -do "run -all" ;;
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isim )
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isim )
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# Xilinx simulator
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# Xilinx simulator
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rm -rf fuse* isim*
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rm -rf fuse* isim*
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fuse tb_openMSP430_fpga glbl -mt off -v 1 -prj $3 -o isim.exe -i ../../../bench/verilog/ -i ../../../rtl/verilog/openmsp430/ -i ../../../rtl/verilog/openmsp430/periph/
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fuse tb_openMSP430 -prj $3 -o isim.exe -i ../../../bench/verilog/ -i ../../../rtl/verilog/ -i ../../../rtl/verilog/periph/
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echo "run all" > isim.tcl
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echo "run all" > isim.tcl
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./isim.exe -tclbatch isim.tcl
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./isim.exe -tclbatch isim.tcl
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exit
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exit
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esac
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esac
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